summaryrefslogtreecommitdiffstats
path: root/drivers/clk/rockchip
Commit message (Expand)AuthorAgeFilesLines
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2024-01-121-0/+3
|\
| * clk: rockchip: rk3568: Mark pclk_usb as criticalChris Morgan2023-12-051-0/+1
| * clk: rockchip: rk3568: Add PLL rate for 126.4MHzChris Morgan2023-12-051-0/+1
| * clk: rockchip: rk3568: Add PLL rate for 115.2MHzChris Morgan2023-11-161-0/+1
* | clk: rockchip: rk3128: Fix SCLK_SDMMC's clock nameAlex Bee2023-11-281-1/+1
* | clk: rockchip: rk3128: Fix aclk_peri_src's parentFinley Xiao2023-11-281-13/+7
* | clk: rockchip: rk3128: Fix HCLK_OTG gate registerWeihao Li2023-11-161-1/+1
* | clk: rockchip: rk3568: Add PLL rate for 292.5MHzChris Morgan2023-11-161-0/+1
|/
* clk: Use device_get_match_data()Rob Herring2023-10-231-7/+2
*-. Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd2023-08-302-1/+61
|\ \
| | * clk: rockchip: rv1126: Add PD_VO clock treeJagan Teki2023-08-101-0/+59
| | * clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHzAlibek Omarov2023-07-101-1/+1
| | * clk: rockchip: rk3568: Add PLL rate for 101MHzAlibek Omarov2023-07-101-0/+1
| |/
* / clk: Explicitly include correct DT includesRob Herring2023-07-192-2/+2
|/
*-. Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into cl...Stephen Boyd2023-04-252-17/+27
|\ \
| | * clk: rockchip: rk3588: make gate linked clocks criticalSebastian Reichel2023-04-181-16/+26
| | * clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparentQuentin Schulz2023-03-071-1/+1
| |/
* / clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_div...Christophe JAILLET2023-04-051-2/+0
|/
*-. Merge branches 'clk-spear', 'clk-fract', 'clk-rockchip' and 'clk-imx' into cl...Stephen Boyd2022-12-129-35/+3795
|\ \
| | * clk: rockchip: Fix memory leak in rockchip_clk_register_pll()Xiu Jianfeng2022-11-231-0/+1
| | * clk: rockchip: add clock controller for the RK3588Elaine Zhang2022-11-155-1/+3447
| | * clk: rockchip: add lookup table supportSebastian Reichel2022-11-142-15/+40
| | * clk: rockchip: simplify rockchip_clk_add_lookupSebastian Reichel2022-11-142-10/+6
| | * clk: rockchip: allow additional mux options for cpu-clock frequency changesElaine Zhang2022-11-142-0/+43
| | * clk: rockchip: add pll type for RK3588Elaine Zhang2022-11-142-1/+235
| | * clk: rockchip: add register offset of the cores select parentElaine Zhang2022-11-142-8/+23
| |/
* / clk: Remove a useless includeChristophe JAILLET2022-11-221-1/+0
|/
* clk: rockchip: Add clock controller support for RV1126 SoCJagan Teki2022-09-234-0/+1165
* clk: rockchip: Add MUXTBL variantElaine Zhang2022-09-132-6/+38
* clk: rockchip: Mark hclk_vo as critical on rk3568Sascha Hauer2022-05-031-0/+1
* clk: rockchip: re-add rational best approximation algorithm to the fractional...Quentin Schulz2022-02-241-0/+3
* clk/rockchip: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)2022-02-231-4/+2
* clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568Sascha Hauer2022-02-081-1/+1
* clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568Sascha Hauer2022-02-081-3/+3
* clk: rockchip: Add more PLL rates for rk3568Sascha Hauer2022-02-081-0/+6
* clk: rockchip: drop module parts from rk3399 and rk3568 driversHeiko Stuebner2021-11-023-10/+2
* Revert "clk: rockchip: use module_platform_driver_probe"Heiko Stuebner2021-11-022-2/+2
* clk: rockchip: use module_platform_driver_probeMiles Chen2021-09-212-2/+2
* clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L}Brian Norris2021-09-201-2/+2
* clk: rockchip: rk3399: make CPU clocks criticalBrian Norris2021-09-201-4/+7
*-. Merge branches 'clk-nvidia', 'clk-rockchip', 'clk-at91' and 'clk-vc5' into cl...Stephen Boyd2021-09-013-3/+5
|\ \
| | * clk: rockchip: make rk3308 ddrphy4x clock criticalYunhao Tian2021-07-291-0/+1
| | * clk: rockchip: drop GRF dependency for rk3328/rk3036 pll typesPeter Geis2021-07-291-1/+1
| | * clk: rockchip: Add support for hclk_sfc on rk3036Jon Lin2021-07-161-1/+1
| | * clk: rockchip: rk3036: fix up the sclk_sfc parent errorJon Lin2021-07-161-1/+2
| |/
* / clk: fractional-divider: Export approximation algorithm to the CCF usersAndy Shevchenko2021-08-121-14/+3
|/
* clk: rockchip: export ACLK_VCODEC for RK3036Alex Bee2021-05-281-1/+1
* clk: rockchip: fix rk3568 cpll clk gate bitsPeter Geis2021-05-241-5/+5
* clk: rockchip: Optimize PLL table memory usageElaine Zhang2021-05-111-11/+18
* clk: rockchip: drop MODULE_ALIAS from rk3399 clock controllerHeiko Stuebner2021-03-211-1/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-25 07:21:46 +0000