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path: root/drivers/clk/st/clkgen-pll.c
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* clk: st: clkgen-pll: embed soc clock outputs within compatible dataAlain Volmat2021-06-271-14/+106
* clk: st: clkgen-pll: remove unused variable of struct clkgen_pllAlain Volmat2021-06-271-1/+0
* clk: st: clkgen-pll: Demote unpopulated kernel-doc headerLee Jones2021-02-111-2/+1
* clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'YueHaibing2019-09-061-13/+0
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner2019-05-301-6/+1
* clk: st: Remove usage of CLK_IS_BASICStephen Boyd2018-12-101-1/+1
* treewide: kzalloc() -> kcalloc()Kees Cook2018-06-121-1/+1
* drivers: clk: st: Simplify clock binding of STiH4xx platformsGabriel Fernandez2016-09-161-34/+29
* drivers: clk: st: Remove stih415-416 clock supportGabriel Fernandez2016-09-161-419/+0
* clk: st: clkgen-pll: Detect critical clocksLee Jones2016-06-301-10/+17
* drivers: clk: st: Correct the pll-type for A9 for stih418Gabriel Fernandez2015-10-081-0/+194
* drivers: clk: st: PLL rate change implementation for DVFSGabriel Fernandez2015-10-081-10/+211
* drivers: clk: st: Support for enable/disable in Clockgen PLLsGabriel Fernandez2015-10-081-1/+59
* drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_xGabriel Fernandez2015-09-171-6/+6
* clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd2015-08-241-4/+4
* Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd2015-07-281-0/+1
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| * clk: st: Include clk.hStephen Boyd2015-07-201-0/+1
* | drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocksPankaj Dev2015-07-061-1/+1
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* clk: st: Silence sparse warningsStephen Boyd2015-05-141-5/+5
* clk: constify of_device_id arrayFabian Frederick2015-04-011-2/+2
* clk: st: STiH407: Support for clockgenA9Gabriel FERNANDEZ2014-07-281-0/+16
* clk: st: STiH407: Support for clockgenC0Gabriel FERNANDEZ2014-07-281-0/+32
* clk: st: STiH407: Support for clockgenA0Gabriel FERNANDEZ2014-07-281-0/+16
* clk: st: use static const for clkgen_pll_data tablesGabriel FERNANDEZ2014-07-281-16/+14
* clk: st: Terminate of match tableStephen Boyd2014-05-281-0/+1
* clk: st: Fix memory leakValentin Ilie2014-05-231-1/+3
* clk: st: Support for ClockGenA9/DDR/GPUGabriel FERNANDEZ2014-03-251-0/+139
* clk: st: Support for PLLs inside ClockGenA(s)Gabriel FERNANDEZ2014-03-251-0/+559
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