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path: root/drivers/clk/tegra/clk-dfll.c
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* clk: tegra: fix old-style declarationArnd Bergmann2021-08-291-1/+1
* clk: tegra: Do not return 0 on failureNicolin Chen2020-11-201-2/+2
* clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()Sowjanya Komatineni2020-01-101-2/+1
* clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni2019-11-111-0/+56
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-301-10/+1
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-03-141-9/+9
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| * clk: tegra: dfll: Fix debugfs_simple_attr.cocci warningsYueHaibing2019-02-221-9/+9
* | clk: tegra: dfll: round down voltages based on alignmentJoseph Lo2019-02-061-8/+13
* | clk: tegra: dfll: support PWM regulator controlJoseph Lo2019-02-061-67/+377
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* clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macroYangtao Li2018-11-281-11/+1
* clk: tegra: probe deferral error reportingMarcel Ziswiler2018-10-161-2/+6
* clk: tegra: no need to check return value of debugfs_create functionsGreg Kroah-Hartman2018-06-011-31/+11
* clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen2017-11-011-5/+5
* PM / OPP: Update OPP users to put referenceViresh Kumar2017-01-301-11/+6
* clk: tegra: dfll: Reference CVB table instead of copying dataThierry Reding2016-04-281-5/+6
* clk: tegra: Remove CLK_IS_ROOTStephen Boyd2016-03-021-1/+0
* Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Michael Turquette2015-10-201-57/+57
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| * clk: tegra: dfll: Monitor code is DEBUG_FS onlyThierry Reding2015-10-201-50/+49
| * clk: tegra: Unlock top rates for Tegra124 DFLL clockMikko Perttunen2015-09-151-7/+8
* | clk: tegra: dfll: Properly protect OPP listThierry Reding2015-09-161-1/+7
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* clk: tegra: Fix some static checker problemsStephen Boyd2015-08-251-3/+5
* clk: tegra: Add Tegra124 DFLL clocksource platform driverTuomas Tynkkynen2015-07-161-3/+3
* clk: tegra: Add closed loop support for the DFLLTuomas Tynkkynen2015-07-161-3/+663
* clk: tegra: Add library for the DFLL clock source (open-loop mode)Tuomas Tynkkynen2015-07-161-0/+1095