Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | clk: tegra: dfll: CVB calculation alignment with the regulator | Joseph Lo | 2019-02-06 | 1 | -1/+5 |
* | clk: tegra: dfll: Fix drvdata overwriting issue | Nicolin Chen | 2017-11-01 | 1 | -1/+1 |
* | clk: tegra: dfll: Properly clean up on failure and removal | Thierry Reding | 2016-04-28 | 1 | -0/+2 |
* | clk: tegra: dfll: Reference CVB table instead of copying data | Thierry Reding | 2016-04-28 | 1 | -8/+2 |
* | clk: tegra: dfll: Update kerneldoc | Thierry Reding | 2016-04-28 | 1 | -5/+5 |
* | clk: tegra: Add Tegra124 DFLL clocksource platform driver | Tuomas Tynkkynen | 2015-07-16 | 1 | -1/+1 |
* | clk: tegra: Add library for the DFLL clock source (open-loop mode) | Tuomas Tynkkynen | 2015-07-16 | 1 | -0/+54 |