summaryrefslogtreecommitdiffstats
path: root/drivers/clk/tegra/clk-tegra210.c
Commit message (Expand)AuthorAgeFilesLines
* clk: tegra: Add PLLE HW power sequencer controlJC Kuo2021-03-241-1/+52
* clk: tegra: Add Tegra210 CSI TPG clock gateSowjanya Komatineni2020-05-121-0/+7
* clk: tegra: Remove the old emc_mux clock for Tegra210Joseph Lo2020-05-121-19/+31
* clk: tegra: Export functions for EMC clock scalingJoseph Lo2020-05-121-0/+26
* clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo2020-05-121-0/+11
* clk: tegra: Use NULL for pointer initializationStephen Boyd2020-03-241-1/+1
* clk: tegra: Remove audio clocks configuration from clock driverSowjanya Komatineni2020-03-121-3/+2
* clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni2020-03-121-14/+3
* clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni2020-03-121-4/+0
* clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni2020-03-121-0/+2
* clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni2020-03-121-0/+4
* clk: tegra: Fix build error without CONFIG_PM_SLEEPYueHaibing2019-11-111-0/+2
* clk: tegra: Add suspend and resume support on Tegra210Sowjanya Komatineni2019-11-111-4/+92
* clk: tegra: Use fence_udelay() during PLLU initSowjanya Komatineni2019-11-111-4/+4
* clk: tegra: Reimplement SOR clocks on Tegra210Thierry Reding2019-11-111-16/+55
* clk: tegra: Rename sor0_lvds to sor0_outThierry Reding2019-11-111-1/+1
* clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRCThierry Reding2019-11-111-1/+1
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-8/+12
|\
| * clk: tegra: Do not enable PLL_RE_VCO on Tegra210Thierry Reding2019-06-251-1/+0
| * clk: tegra: Warn if an enabled PLL is in IDDQThierry Reding2019-06-251-1/+5
| * clk: tegra: Do not warn unnecessarilyThierry Reding2019-06-251-2/+3
| * clk: tegra210: fix PLLU and PLLU_OUT1JC Kuo2019-06-251-4/+4
* | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2019-06-281-0/+2
|\ \
| * | clk: tegra210: Fix default rates for HDA clocksJon Hunter2019-06-141-0/+2
| |/
* / treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1
|/
* clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski2019-04-231-3/+3
* clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter2018-12-141-1/+8
* clk: tegra210: Include size.h for compilation easeStephen Boyd2018-10-161-0/+1
* clk: tegra: Fixes for MBIST work aroundJoseph Lo2018-10-161-3/+3
* clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver2018-07-251-2/+12
* clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko2018-05-181-1/+1
* clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko2018-03-121-2/+1
* clk: tegra: MBIST work around for Tegra210Peter De Schrijver2018-03-081-2/+342
* clk: tegra: Add la clock for Tegra210Peter De Schrijver2018-03-081-0/+14
* clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen2017-11-011-2/+2
* clk: tegra: Fix sor1_out clock implementationThierry Reding2017-10-191-0/+47
* clk: tegra: Fix Tegra210 PLLU initializationAlex Frid2017-08-231-2/+4
* clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid2017-08-231-3/+3
* clk: tegra: Re-factor T210 PLLX registrationAlex Frid2017-08-231-1/+1
* clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver2017-08-231-2/+4
* clk: tegra: Fix T210 effective NDIV calculationAlex Frid2017-08-231-4/+5
* clk: tegra210: remove non-existing VFIR clockPeter De Schrijver2017-08-231-1/+0
* clk: tegra: disable SSC for PLL_D2Peter De Schrijver2017-08-231-1/+1
* clk: tegra: Don't reset PLL-CX if it is already enabledJon Hunter2017-04-041-4/+4
* clk: tegra: Add missing Tegra210 clocksPeter De Schrijver2017-04-041-0/+7
* clk: tegra: Mark TEGRA210_CLK_DBGAPB as always onPeter De Schrijver2017-03-201-0/+2
* clk: tegra: Add SATA seq input controlPeter De Schrijver2017-03-201-0/+25
* clk: tegra: Add Tegra210 special resetsPeter De Schrijver2017-03-201-0/+85
* clk: tegra: Rework pll_uPeter De Schrijver2017-03-201-23/+272
* clk: tegra: Handle UTMIPLL IDDQPeter De Schrijver2017-03-201-0/+26
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 11:45:28 +0000