linux-stable.git - Linux kernel stable tree

	Commit message (Expand)	Author	Age	Files	Lines
*	clk: tegra210: fix PLLU and PLLU_OUT1	JC Kuo	2019-08-06	1	-4/+4
*	clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider	Dmitry Osipenko	2019-05-25	1	-2/+2
*	clk: tegra: bpmp: Don't crash when a clock fails to register	Mikko Perttunen	2018-09-26	1	-3/+9
*	clk: tegra: Fix pll_u rate configuration	Marcel Ziswiler	2018-05-25	1	-0/+2
*	clk: tegra: Fix cclk_lp divisor register	Michał Mirosław	2017-12-20	1	-1/+1
*	clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()	Nicolin Chen	2017-12-20	1	-2/+2
*	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	Greg Kroah-Hartman	2017-11-02	2	-0/+2
*	clk: tegra: Fix Tegra210 PLLU initialization	Alex Frid	2017-08-23	1	-2/+4
*	clk: tegra: Correct Tegra210 UTMIPLL poweron delay	Alex Frid	2017-08-23	1	-3/+3
*	clk: tegra: Fix T210 PLLRE registration	Alex Frid	2017-08-23	1	-20/+1
*	clk: tegra: Update T210 PLLSS (D2/DP) registration	Alex Frid	2017-08-23	1	-39/+9
*	clk: tegra: Re-factor T210 PLLX registration	Alex Frid	2017-08-23	4	-49/+10
*	clk: tegra: don't warn for pll_d2 defaults unnecessarily	Peter De Schrijver	2017-08-23	1	-2/+4
*	clk: tegra: change post IDDQ release delay to 5us	Peter De Schrijver	2017-08-23	1	-1/+1
*	clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C	Alex Frid	2017-08-23	1	-1/+2
*	clk: tegra: Fix T210 effective NDIV calculation	Alex Frid	2017-08-23	1	-4/+5
*	clk: tegra: Init cfg structure in _get_pll_mnp	Peter De Schrijver	2017-08-23	1	-0/+2
*	clk: tegra210: remove non-existing VFIR clock	Peter De Schrijver	2017-08-23	1	-1/+0
*	clk: tegra: disable SSC for PLL_D2	Peter De Schrijver	2017-08-23	1	-1/+1
*	clk: tegra: Enable PLL_SS for Tegra210	Peter De Schrijver	2017-08-23	1	-1/+1
*	clk: tegra: fix SS control on PLL enable/disable	Peter De Schrijver	2017-08-23	1	-20/+24
*	clk: Convert to using %pOF instead of full_name	Rob Herring	2017-07-21	1	-7/+5
*	clk: tegra: Don't reset PLL-CX if it is already enabled	Jon Hunter	2017-04-04	1	-4/+4
*	clk: tegra: Add missing Tegra210 clocks	Peter De Schrijver	2017-04-04	3	-0/+19
*	clk: tegra: Propagate clk_out_x rate to parent	Alex Frid	2017-04-04	1	-2/+4
*	clk: tegra: Fix build warnings on Tegra20/Tegra30	Thierry Reding	2017-03-20	2	-2/+2
*	clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on	Peter De Schrijver	2017-03-20	1	-0/+2
*	clk: tegra: Add SATA seq input control	Peter De Schrijver	2017-03-20	1	-0/+25
*	clk: tegra: Add Tegra210 special resets	Peter De Schrijver	2017-03-20	1	-0/+85
*	clk: tegra: Rework pll_u	Peter De Schrijver	2017-03-20	2	-197/+272
*	clk: tegra: Implement reset control reset	Mikko Perttunen	2017-03-20	1	-0/+16
*	clk: tegra: Fix disable unused for clocks sharing enable bit	Peter De Schrijver	2017-03-20	1	-0/+3
*	clk: tegra: Handle UTMIPLL IDDQ	Peter De Schrijver	2017-03-20	1	-0/+26
*	clk: tegra: Add aclk	Peter De Schrijver	2017-03-20	1	-0/+10
*	clk: tegra: Add super clock mux/divider	Peter De Schrijver	2017-03-20	2	-5/+89
*	clk: tegra: Define Tegra210 DMIC clocks	Peter De Schrijver	2017-03-20	3	-1/+28
*	clk: tegra: Fix constness for peripheral clocks	Peter De Schrijver	2017-03-20	2	-4/+4
*	clk: tegra: Define Tegra210 DMIC sync clocks	Peter De Schrijver	2017-03-20	3	-24/+73
*	clk: tegra: Add CEC clock	Peter De Schrijver	2017-03-20	6	-0/+6
*	clk: tegra: Fix type for m field	Peter De Schrijver	2017-03-20	1	-1/+1
*	clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation	Peter De Schrijver	2017-03-20	1	-1/+7
*	clk: tegra: Don't warn for PLL defaults unnecessarily	Peter De Schrijver	2017-03-20	1	-6/+12
*	clk: tegra: Remove non-existing pll_m_out1 clock	Peter De Schrijver	2017-03-20	1	-5/+0
*	clk: tegra: Correct afi clock parent	Peter De Schrijver	2017-03-20	1	-1/+1
*	clk: tegra: Fix ISP clock modelling	Peter De Schrijver	2017-03-20	3	-2/+11
*	clk: tegra: Fix pll_a1 iddq register, add pll_a1	Peter De Schrijver	2017-03-20	1	-1/+2
*	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	2017-02-25	3	-0/+625
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\| *	clk: tegra: Add BPMP clock driver	Thierry Reding	2017-02-03	3	-0/+625
* \|	PM / OPP: Update OPP users to put reference	Viresh Kumar	2017-01-30	1	-11/+6
\|/
*	clk: tegra: dfll: Use builtin_platform_driver to simplify the code	Wei Yongjun	2016-11-10	1	-6/+1