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path: root/drivers/clk/tegra
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* clk: tegra: fix error return case for recalc_rateTimo Alho2023-10-101-1/+1
* clk: tegra: tegra124-emc: Fix potential memory leakYuan Can2023-07-271-0/+2
* clk: tegra20: fix gcc-7 constant overflow warningArnd Bergmann2023-05-301-14/+14
* clk: tegra20: Fix refcount leak in tegra20_clock_initMiaoqian Lin2022-10-261-0/+1
* clk: tegra: Fix refcount leak in tegra114_clock_initMiaoqian Lin2022-10-261-0/+1
* clk: tegra: Fix refcount leak in tegra210_clock_initMiaoqian Lin2022-10-261-0/+1
* clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driverMiaoqian Lin2022-04-151-0/+1
* clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko2021-07-191-5/+4
* clk: tegra30: Add hda clock default rates to clock driverPeter Geis2021-01-271-0/+2
* clk: tegra: Do not return 0 on failureNicolin Chen2020-12-301-2/+2
* clk: tegra: Fix duplicated SE clock entryDmitry Osipenko2020-12-302-1/+2
* clk: tegra: Always program PLL_E when enabledThierry Reding2020-10-071-3/+0
* clk: tegra: Fix Tegra PMC clock out parentsSowjanya Komatineni2020-04-231-6/+6
* clk: tegra: Mark fuse clock as criticalStephen Warren2020-02-111-1/+5
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-8/+12
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| * clk: tegra: Do not enable PLL_RE_VCO on Tegra210Thierry Reding2019-06-251-1/+0
| * clk: tegra: Warn if an enabled PLL is in IDDQThierry Reding2019-06-251-1/+5
| * clk: tegra: Do not warn unnecessarilyThierry Reding2019-06-251-2/+3
| * clk: tegra210: fix PLLU and PLLU_OUT1JC Kuo2019-06-251-4/+4
* | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2019-06-281-0/+2
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| * | clk: tegra210: Fix default rates for HDA clocksJon Hunter2019-06-141-0/+2
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* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner2019-06-051-9/+1
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-3020-240/+20
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-305-49/+5
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
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* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-154-0/+4
*-. Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd2019-05-074-40/+77
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| | * clk: tegra: divider: Mark Memory Controller clock as read-onlyDmitry Osipenko2019-04-251-1/+2
| | * clk: tegra: emc: Replace BUG() with WARN_ONCE()Dmitry Osipenko2019-04-251-1/+4
| | * clk: tegra: emc: Fix EMC max-rate clampingDmitry Osipenko2019-04-251-7/+10
| | * clk: tegra: emc: Support multiple RAM codesDmitry Osipenko2019-04-251-14/+23
| | * clk: tegra: emc: Don't enable EMC clock manuallyDmitry Osipenko2019-04-251-2/+0
| | * clk: tegra124: Remove lock-enable bit from PLLMDmitry Osipenko2019-04-251-2/+1
| | * clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko2019-04-251-2/+2
| | * clk: tegra: Don't enable already enabled PLLsDmitry Osipenko2019-04-191-13/+37
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*-. | Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd2019-05-071-1/+1
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| * | clk: tegra: Make tegra_clk_super_mux_ops staticYueHaibing2019-04-111-1/+1
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* / clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski2019-04-232-5/+5
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-03-141-9/+9
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| *-. Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ...Stephen Boyd2019-03-081-9/+9
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| | | * clk: tegra: dfll: Fix debugfs_simple_attr.cocci warningsYueHaibing2019-02-221-9/+9
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* | | clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' staticWei Yongjun2019-02-181-1/+1
* | | Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Arnd Bergmann2019-02-157-98/+913
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| * | clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Peter De Schrijver2019-02-062-1/+6
| * | clk: tegra: dfll: add CVB tables for Tegra210Joseph Lo2019-02-062-0/+427
| * | clk: tegra: dfll: round down voltages based on alignmentJoseph Lo2019-02-061-8/+13
| * | clk: tegra: dfll: support PWM regulator controlJoseph Lo2019-02-061-67/+377
| * | clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo2019-02-064-14/+59
| * | clk: tegra: dfll: registration for multiple SoCsPeter De Schrijver2019-02-061-11/+34
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