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path: root/drivers/clk/tegra
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-10-221-1/+1
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| * clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()Stephen Boyd2020-09-231-1/+1
* | clk: tegra: Fix missing prototype for tegra210_clk_register_emc()Thierry Reding2020-09-211-0/+2
* | clk: tegra: Always program PLL_E when enabledThierry Reding2020-09-211-3/+0
* | clk: tegra: Capitalization fixesThierry Reding2020-09-211-2/+2
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* clk: tegra: pll: Improve PLLM enable-state detectionDmitry Osipenko2020-07-271-5/+15
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-06-1010-32/+700
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| * clk: tegra: Add Tegra210 CSI TPG clock gateSowjanya Komatineni2020-05-121-0/+7
| * clk: tegra30: Use custom CCLK implementationDmitry Osipenko2020-05-121-2/+4
| * clk: tegra20: Use custom CCLK implementationDmitry Osipenko2020-05-121-2/+5
| * clk: tegra: cclk: Add helpers for handling PLLX rate changesDmitry Osipenko2020-05-122-0/+36
| * clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko2020-05-122-1/+17
| * clk: tegra: Add custom CCLK implementationDmitry Osipenko2020-05-123-2/+188
| * clk: tegra: Remove the old emc_mux clock for Tegra210Joseph Lo2020-05-121-19/+31
| * clk: tegra: Implement Tegra210 EMC clockJoseph Lo2020-05-123-0/+373
| * clk: tegra: Export functions for EMC clock scalingJoseph Lo2020-05-121-0/+26
| * clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo2020-05-121-0/+11
| * clk: tegra: Rename Tegra124 EMC clock source fileThierry Reding2020-05-124-6/+2
* | clk: tegra: Fix initial rate for pll_a on Tegra124Thierry Reding2020-05-121-1/+1
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* clk: tegra: Use NULL for pointer initializationStephen Boyd2020-03-241-1/+1
* clk: tegra: Remove audio clocks configuration from clock driverSowjanya Komatineni2020-03-125-15/+10
* clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni2020-03-129-201/+19
* clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni2020-03-126-45/+0
* clk: tegra: Fix Tegra PMC clock out parentsSowjanya Komatineni2020-03-121-6/+6
* clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni2020-03-126-0/+14
* clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni2020-03-126-0/+34
*-. Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', '...Stephen Boyd2020-01-315-11/+15
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| | * clk: tegra20/30: Explicitly set parent clock for Video DecoderDmitry Osipenko2020-01-102-2/+2
| | * clk: tegra20/30: Don't pre-initialize displays parent clockDmitry Osipenko2020-01-102-4/+0
| | * clk: tegra: divider: Check UART's divider enable-bit state on rate's recalcul...Dmitry Osipenko2020-01-101-2/+7
| | * clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()Sowjanya Komatineni2020-01-101-2/+1
| | * clk: tegra: Mark fuse clock as criticalStephen Warren2020-01-081-1/+5
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* / clk: tegra: Fix double-free in tegra_clk_init()Dmitry Osipenko2019-12-241-1/+3
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* clk: tegra: Use match_string() helper to simplify the codeYueHaibing2019-11-131-8/+4
* clk: tegra: Fix build error without CONFIG_PM_SLEEPYueHaibing2019-11-111-0/+2
* clk: tegra: Optimize PLLX restore on Tegra20/30Dmitry Osipenko2019-11-112-18/+32
* clk: tegra: Add suspend and resume support on Tegra210Sowjanya Komatineni2019-11-113-4/+163
* clk: tegra: Share clk and rst register defines with Tegra clock driverSowjanya Komatineni2019-11-112-45/+45
* clk: tegra: Use fence_udelay() during PLLU initSowjanya Komatineni2019-11-111-4/+4
* clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni2019-11-113-0/+59
* clk: tegra: clk-super: Add restore-context supportSowjanya Komatineni2019-11-111-0/+27
* clk: tegra: clk-super: Fix to enable PLLP branches to CPUSowjanya Komatineni2019-11-114-1/+39
* clk: tegra: periph: Add restore_context supportSowjanya Komatineni2019-11-112-0/+37
* clk: tegra: Support for OSC context save and restoreSowjanya Komatineni2019-11-112-0/+16
* clk: tegra: pll: Save and restore pll contextSowjanya Komatineni2019-11-111-32/+54
* clk: tegra: pllout: Save and restore pllout contextSowjanya Komatineni2019-11-111-0/+9
* clk: tegra: divider: Save and restore divider rateSowjanya Komatineni2019-11-111-0/+11
* clk: tegra: Reimplement SOR clocks on Tegra210Thierry Reding2019-11-111-16/+55
* clk: tegra: Reimplement SOR clock on Tegra124Thierry Reding2019-11-111-9/+13
* clk: tegra: Rename sor0_lvds to sor0_outThierry Reding2019-11-113-8/+8
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