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* clk: ast2600: Fix AHB clock divider for A1Eddie James2020-06-241-6/+25
* clk: sprd: return correct type of value for _sprd_pll_recalc_rateChunyan Zhang2020-06-241-1/+1
* clk: bcm2835: Fix return type of bcm2835_register_gateNathan Chancellor2020-06-241-5/+5
* clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1Marek Szyprowski2020-06-241-1/+2
* clk: ti: composite: fix memory leakTero Kristo2020-06-241-0/+1
* clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl2020-06-242-0/+13
* clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl2020-06-241-5/+5
* clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl2020-06-241-23/+56
* clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl2020-06-241-1/+1
* clk: clk-flexgen: fix clock-critical handlingAlain Volmat2020-06-241-0/+1
* clk: zynqmp: fix memory leak in zynqmp_register_clocksQuanyang Wang2020-06-241-6/+9
* clk: renesas: cpg-mssr: Fix STBCR suspend/resume handlingGeert Uytterhoeven2020-06-241-3/+5
* clk: samsung: Mark top ISP and CAM clocks on Exynos542x as criticalMarek Szyprowski2020-06-241-7/+9
* clk: qcom: msm8916: Fix the address location of pll->config_regBryan O'Donoghue2020-06-241-4/+4
* clk: sunxi: Fix incorrect usage of round_down()Rikard Falkeborn2020-06-241-1/+1
* clk: mediatek: assign the initial value to clk_init_data of mtk_muxWeiyi Lu2020-06-221-1/+1
* PM: runtime: clk: Fix clk_pm_runtime_get() error pathRafael J. Wysocki2020-06-171-1/+5
* clk: qcom: gcc: Fix parent for gpll0_out_evenVinod Koul2020-06-031-2/+1
* clk: ti: am33xx: fix RTC clock parentTero Kristo2020-06-031-1/+1
* clk: Unlink clock if failed to prepare or enableMarc Zyngier2020-05-201-0/+3
* clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocksJustin Swartz2020-05-201-13/+4
* clk: tegra: Fix Tegra PMC clock out parentsSowjanya Komatineni2020-04-231-6/+6
* clk: at91: usb: continue if clk_hw_round_rate() return zeroClaudiu Beznea2020-04-231-0/+3
* clk: Don't cache errors from clk_ops::get_phase()Stephen Boyd2020-04-231-16/+32
* clk: at91: usb: use proper usbs_maskClaudiu Beznea2020-04-211-1/+1
* clk: at91: sam9x60: fix usb clock parentsClaudiu Beznea2020-04-211-3/+2
* clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil2020-04-171-1/+1
* clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil2020-04-171-1/+3
* clk: ti: am43xx: Fix clock parent for RTC clockTony Lindgren2020-04-021-1/+1
* clk: imx: Align imx sc clock parent msg structs to 4Leonard Crestez2020-04-021-1/+1
* clk: imx: Align imx sc clock msg structs to 4Leonard Crestez2020-04-021-3/+3
* clk: uniphier: Add SCSSI clock gate for each channelKunihiko Hayashi2020-02-241-5/+8
* clk: Use parent node pointer during registration if necessaryStephen Boyd2020-02-241-2/+25
* clk: sunxi-ng: add mux and pll notifiers for A64 CPU clockIcenowy Zheng2020-02-241-1/+27
* clk: actually call the clock init before any other callback of the clockJerome Brunet2020-02-241-11/+15
* clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocksSergei Shtylyov2020-02-241-2/+4
* clk: qcom: smd: Add missing bimc clockJeffrey Hugo2020-02-241-0/+3
* clk: imx: Add correct failure handling for clk based helpersAbel Vesa2020-02-241-15/+22
* clk: qcom: rcg2: Don't crash if our parent can't be found; return an errorDouglas Anderson2020-02-241-0/+3
* clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq()Stephen Boyd2020-02-241-4/+4
* clk: ti: dra7: fix parent for gmac_clkctrlGrygorii Strashko2020-02-241-1/+1
* clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl2020-02-241-4/+7
* clk: at91: sam9x60: fix programmable clock prescalerEugen Hristev2020-02-241-0/+1
* clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel2020-02-241-0/+9
* clk: meson: g12a: fix missing uart2 in regmap tableJerome Brunet2020-02-141-0/+1
* clk: tegra: Mark fuse clock as criticalStephen Warren2020-02-111-1/+5
* clk: mmp2: Fix the order of timer mux parentsLubomir Rintel2020-02-051-1/+1
* clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent orderSamuel Holland2020-02-051-2/+2
* clk: sunxi-ng: sun8i-r: Fix divider on APB0 clockSamuel Holland2020-02-051-18/+3
* clk: sunxi-ng: v3s: Fix incorrect number of hw_clks.Yunhao Tian2020-02-052-4/+2
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