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* clk: at91: generated: consider range when calculating best rateCodrin Ciubotariu2022-05-251-0/+4
* clk: sunxi: sun9i-mmc: check return value after calling platform_get_resource()Yang Yingliang2022-05-091-0/+2
* clk: Enforce that disjoints limits are invalidMaxime Ripard2022-04-151-0/+24
* clk: si5341: fix reported clk_rate when output divider is 2Adam Wujek2022-04-151-7/+9
* clk: Initialize orphan req_rateMaxime Ripard2022-04-151-0/+13
* clk: qcom: gcc-msm8994: Fix gpll4 widthKonrad Dybcio2022-04-151-0/+1
* clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driverMiaoqian Lin2022-04-151-0/+1
* clk: clps711x: Terminate clk_div_table with sentinel elementJonathan Neuschäfer2022-04-151-0/+2
* clk: loongson1: Terminate clk_div_table with sentinel elementJonathan Neuschäfer2022-04-151-0/+1
* clk: actions: Terminate clk_div_table with sentinel elementJonathan Neuschäfer2022-04-152-1/+2
* clk: qcom: clk-rcg2: Update the frac table for pixel clockTaniya Das2022-04-151-0/+1
* clk: qcom: clk-rcg2: Update logic to calculate D value for RCGTaniya Das2022-04-151-2/+11
* clk: imx7d: Remove audio_mclk_root_clkAbel Vesa2022-04-151-1/+0
* clk: qcom: ipq8074: Use floor ops for SDCC1 clockDirk Buchwalder2022-04-151-1/+1
* clk: uniphier: Fix fixed-rate initializationKunihiko Hayashi2022-04-151-0/+1
* clk: qcom: gdsc: Add support to update GDSC transition delayTaniya Das2022-03-162-6/+28
* clk: jz4725b: fix mmc0 clock gatingSiarhei Volkau2022-03-021-2/+1
* clk: si5341: Fix clock HW provider cleanupRobert Hancock2022-01-271-1/+1
* clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBBMartin Blumenstingl2022-01-271-3/+41
* clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system en...Dillon Min2022-01-271-4/+0
* clk: imx8mn: Fix imx8mn_clko1_selsAdam Ford2022-01-271-3/+3
* clk: bcm-2835: Remove rounding up the dividersMaxime Ripard2022-01-271-8/+3
* clk: bcm-2835: Pick the closest clock rateMaxime Ripard2022-01-271-1/+1
* clk: Don't parent clks until the parent is fully registeredMike Tipton2021-12-221-3/+12
* clk: qcom: regmap-mux: fix parent clock lookupDmitry Baryshkov2021-12-143-1/+15
* clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clkDmitry Baryshkov2021-11-261-15/+0
* clk/ast2600: Fix soc revision for AHBJoel Stanley2021-11-261-5/+7
* clk: ingenic: Fix bugs with divided dividersPaul Cercueil2021-11-261-3/+3
* clk: imx: imx6ul: Move csi_sel mux to correct base registerStefan Riedmueller2021-11-261-1/+1
* clk: at91: check pmc node status before registering syscore opsClément Léger2021-11-171-0/+5
* clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling pathsChristophe JAILLET2021-11-171-3/+11
* clk: at91: clk-generated: Limit the requested rate to our rangeCodrin Ciubotariu2021-09-221-0/+6
* clk: at91: clk-generated: pass the id of changeable parent at registrationClaudiu Beznea2021-09-225-35/+37
* clk: at91: sam9x60: Don't use audio PLLCodrin Ciubotariu2021-09-221-6/+3
* clk: kirkwood: Fix a clocking boot regressionLinus Walleij2021-09-151-0/+1
* clk: fix leak on devm_clk_bulk_get_all() unwindBrian Norris2021-08-121-1/+8
* clk: stm32f4: fix post divisor setup for I2S/SAI PLLsDario Binacchi2021-08-121-5/+5
* clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko2021-07-191-5/+4
* clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto2021-07-191-0/+1
* clk: si5341: Update initialization magicRobert Hancock2021-07-141-1/+3
* clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock2021-07-141-2/+13
* clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea2021-07-141-15/+29
* clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea2021-07-141-4/+2
* clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea2021-07-141-6/+6
* clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet2021-07-141-1/+1
* clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940Tony Lindgren2021-06-231-0/+1
* clk: exynos7: Mark aclk_fsys1_200 as criticalPaweł Chmiel2021-05-191-1/+6
* clk: uniphier: Fix potential infinite loopColin Ian King2021-05-141-2/+2
* clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLEChen Hui2021-05-141-0/+1
* clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callbackQuanyang Wang2021-05-141-6/+6