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* clk: ti: clkctrl: Fix clkdm_clk handlingTony Lindgren2019-06-221-4/+4
* clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288Douglas Anderson2019-06-151-0/+11
* clk: rockchip: Make rkpwm a critical clock on rk3288Douglas Anderson2019-05-311-1/+3
* clk: rockchip: Fix video codec clocks on rk3288Douglas Anderson2019-05-311-2/+2
* clk: rockchip: undo several noc and special clocks as critical on rk3288Douglas Anderson2019-05-311-9/+4
* clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0)Jernej Skrabec2019-05-251-5/+13
* clk: rockchip: fix wrong clock definitions for rk3328Jonas Karlman2019-05-251-9/+9
* clk: mediatek: Disable tuner_en before change PLL rateOwen Chen2019-05-251-14/+34
* clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko2019-05-251-2/+2
* clk: hi3660: Mark clk_gate_ufs_subsys as criticalLeo Yan2019-05-251-1/+5
* clk: meson-gxbb: round the vdec dividers to closestMaxime Jourdan2019-05-101-0/+2
* clk: x86: Add system specific quirk to mark clocks as criticalDavid Müller2019-05-081-3/+11
* clk: qcom: Add missing freq for usb30_master_clk on 8998Jeffrey Hugo2019-05-081-0/+1
* Revert "clk: meson: clean-up clock registration"Neil Armstrong2019-04-171-10/+5
* clk: rockchip: fix frac settings of GPLL clock for rk3328Katsuhiro Suzuki2019-04-051-6/+6
* clk: meson: clean-up clock registrationJerome Brunet2019-04-051-5/+10
* clk: fractional-divider: check parent rate only if flag is setKatsuhiro Suzuki2019-04-051-1/+1
* clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil2019-03-231-1/+1
* clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil2019-03-231-5/+5
* clk: samsung: exynos5: Fix kfree() of const memory on setting driver_overrideKrzysztof Kozlowski2019-03-231-2/+1
* clk: samsung: exynos5: Fix possible NULL pointer exception on platform_device...Krzysztof Kozlowski2019-03-231-2/+8
* clk: clk-twl6040: Fix imprecise external abort for pdmclkTony Lindgren2019-03-231-2/+51
* clk: uniphier: Fix update register for CPU-gearKunihiko Hayashi2019-03-231-1/+1
* clk: sunxi: A31: Fix wrong AHB gate numberAndre Przywara2019-03-231-2/+2
* clk: sunxi-ng: v3s: Fix TCON reset de-assert bitPaul Kocialkowski2019-03-231-1/+1
* clk: qcom: gcc: Use active only source for CPUSS clocksTaniya Das2019-03-131-4/+10
* clk: ti: Fix error handling in ti_clk_parse_divider_data()Dan Carpenter2019-03-131-1/+10
* clk: vc5: Abort clock configuration without upstream clockMarek Vasut2019-03-051-1/+3
* clk: sysfs: fix invalid JSON in clk_dumpLubomir Rintel2019-03-051-1/+1
* clk: tegra: dfll: Fix a potential Oop in remove()Dan Carpenter2019-03-051-1/+3
* clk: imx6sl: ensure MMDC CH0 handshake is bypassedAnson Huang2019-02-121-0/+6
* clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocksChen-Yu Tsai2019-02-121-3/+3
* clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICALMartin Blumenstingl2019-02-121-1/+2
* clk: meson: meson8b: fix the width of the cpu_scale_div clockMartin Blumenstingl2019-02-121-1/+1
* clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_selMartin Blumenstingl2019-02-121-2/+9
* clk: boston: fix possible memory leak in clk_boston_setup()Yi Wang2019-02-121-3/+8
* clk: socfpga: stratix10: fix naming convention for the fixed-clocksDinh Nguyen2019-01-311-10/+10
* clk: socfpga: stratix10: fix rate calculation for pll clocksDinh Nguyen2019-01-311-1/+1
* clk: imx6q: reset exclusive gates on initLucas Stach2019-01-261-1/+5
* clk: imx: make mux parent strings constA.s. Dong2019-01-263-9/+13
* clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_tableMartin Blumenstingl2019-01-261-7/+8
* clk: sunxi-ng: Use u64 for calculation of NM rateJernej Skrabec2019-01-091-3/+15
* clk: rockchip: fix typo in rk3188 spdif_frac parentJohan Jonker2019-01-091-1/+1
* clk: mmp: Off by one in mmp_clk_add()Dan Carpenter2018-12-211-1/+1
* clk: mvebu: Off by one bugs in cp110_of_clk_get()Dan Carpenter2018-12-211-2/+2
* clk: fixed-factor: fix of_node_get-put imbalanceRicardo Ribalda Delgado2018-11-271-0/+1
* clk: ti: fix OF child-node lookupJohan Hovold2018-11-271-4/+9
* clk: renesas: r9a06g032: Fix UART34567 clock ratePhil Edworthy2018-11-271-1/+2
* clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet2018-11-273-8/+8
* clk: meson-axg: pcie: drop the mpll3 clock parentYixun Lan2018-11-271-2/+4
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