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| | * | clk: qcom: gcc-qcm2290: Mark RCGs shared where applicableKonrad Dybcio2023-05-241-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vast majority of shared RCGs were not marked as such. Fix it. Fixes: 496d1a13d405 ("clk: qcom: Add Global Clock Controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230403174807.345185-1-konrad.dybcio@linaro.org
| | * | clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550Jagadeesh Kona2023-05-243-0/+481
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the video clock controller for video clients to be able to request for videocc clocks on SM8550 platform. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524145203.13153-4-quic_jkona@quicinc.com
| | * | clk: qcom: clk-alpha-pll: Add support to configure PLL_TEST_CTL_U2Jagadeesh Kona2023-05-242-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lucid ole pll reuses lucid evo ops but it has an additional test control register which is required to be programmed, add support to program the same. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524145203.13153-2-quic_jkona@quicinc.com
| | * | clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450Taniya Das2023-05-243-0/+473
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the video clock controller driver for peripheral clock clients to be able to request for video cc clocks. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524140656.7076-3-quic_tdas@quicinc.com
| | * | clk: qcom: Introduce SM8350 VIDEOCCKonrad Dybcio2023-05-243-0/+562
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Video Clock Controller found on the SM8350 SoC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-2-86c714a66a81@linaro.org
| | * | clk: qcom: gcc-ipq6018: Use floor ops for sdcc clocksMantas Pucka2023-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDCC clocks must be rounded down to avoid overclocking the controller. Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Mantas Pucka <mantas@8devices.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1682413909-24927-1-git-send-email-mantas@8devices.com
| | * | clk: qcom: smd-rpm: Make BI_TCXO_AO criticalKonrad Dybcio2023-05-241-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should never let go of the active-only XO vote, as otherwise the RPM may decide that there are no online users and it can be shut down, resulting in a total, uncontrolled system collapse. Guarantee this through adding the CLK_IS_CRITICAL flag. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Matti Lehtimäki <matti.lehtimaki@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501-topic-rpmcc_xo_a-v1-3-93f18e47b607@linaro.org
| | * | clk: qcom: smd-rpm: Make DEFINE_CLK_SMD_RPM_BRANCH_A accept flagsKonrad Dybcio2023-05-241-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for supporting keepalive clocks which can never be shut off (as the platform would fall apart otherwise), make the DEFINE_CLK_SMD_RPM_BRANCH_A macro accept clock flags for the active-only clock. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Matti Lehtimäki <matti.lehtimaki@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501-topic-rpmcc_xo_a-v1-2-93f18e47b607@linaro.org
| | * | clk: qcom: smd-rpm_ Make __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX accept flagsKonrad Dybcio2023-05-241-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for supporting keepalive clocks which can never be shut off (as the platform would fall apart otherwise), make the __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX macro accept clock flags for the active-only clock. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Matti Lehtimäki <matti.lehtimaki@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501-topic-rpmcc_xo_a-v1-1-93f18e47b607@linaro.org
| | * | clk: qcom: smd-rpm: Keep one rpm handle for all clocksKonrad Dybcio2023-05-241-14/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For no apparent reason (as there's just one RPM per SoC), all clocks currently store a copy of a pointer to smd_rpm. Introduce a single, global one to save up on space in each clk definition. bloat-o-meter reports: Total: Before=41887, After=40843, chg -2.49% Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501130400.107771-1-konrad.dybcio@linaro.org
| | * | clk: qcom: camcc-sc7180: Add parent dependency to all camera GDSCsTaniya Das2023-05-241-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Camera titan top GDSC is a parent supply to all other camera GDSCs. Titan top GDSC is required to be enabled before enabling any other camera GDSCs and it should be disabled only after all other camera GDSCs are disabled. Ensure this behavior by marking titan top GDSC as parent of all other camera GDSCs. Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller driver for SC7180") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501142932.13049-1-quic_tdas@quicinc.com
| | * | clk: qcom: mmcc-msm8974: remove oxili_ocmemgx_clkDmitry Baryshkov2023-05-241-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the internal discussions, it looks like this clock is managed by RPM itself. Linux kernel should not touch it on its own, as this causes disagreement with RPM. Shutting down this clock causes the OCMEM<->GPU interface to stop working, resulting in GPU hangchecks/timeouts. Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230508153319.2371645-1-dmitry.baryshkov@linaro.org
| | * | clk: qcom: gcc: ipq5332: Use floor ops for SDCC clocksKathiravan T2023-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDCC clocks must be rounded down to avoid overclocking the controller. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230508163145.9678-1-quic_kathirav@quicinc.com
| | * | clk: qcom: gcc-ipq9574: constify struct clk_init_dataDevi Priya2023-05-171-211/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the clk_init_data struct constant. Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230425084010.15581-5-quic_devipriy@quicinc.com
| | * | clk: qcom: gcc-ipq9574: Clean up included headersDevi Priya2023-05-171-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some included headers aren't actually used anywhere, while other headers with the declaration of functions and structures aren't directly included. Get rid of the unused ones, and add the ones that should be included directly. Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230425084010.15581-4-quic_devipriy@quicinc.com
* | | | Merge tag 'char-misc-6.5-rc1' of ↵Linus Torvalds2023-07-032-1/+60
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull Char/Misc updates from Greg KH: "Here is the big set of char/misc and other driver subsystem updates for 6.5-rc1. Lots of different, tiny, stuff in here, from a range of smaller driver subsystems, including pulls from some substems directly: - IIO driver updates and additions - W1 driver updates and fixes (and a new maintainer!) - FPGA driver updates and fixes - Counter driver updates - Extcon driver updates - Interconnect driver updates - Coresight driver updates - mfd tree tag merge needed for other updates on top of that, lots of small driver updates as patches, including: - static const updates for class structures - nvmem driver updates - pcmcia driver fix - lots of other small driver updates and fixes All of these have been in linux-next for a while with no reported problems" * tag 'char-misc-6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (243 commits) bsr: fix build problem with bsr_class static cleanup comedi: make all 'class' structures const char: xillybus: make xillybus_class a static const structure xilinx_hwicap: make icap_class a static const structure virtio_console: make port class a static const structure ppdev: make ppdev_class a static const structure char: misc: make misc_class a static const structure /dev/mem: make mem_class a static const structure char: lp: make lp_class a static const structure dsp56k: make dsp56k_class a static const structure bsr: make bsr_class a static const structure oradax: make 'cl' a static const structure hwtracing: hisi_ptt: Fix potential sleep in atomic context hwtracing: hisi_ptt: Advertise PERF_PMU_CAP_NO_EXCLUDE for PTT PMU hwtracing: hisi_ptt: Export available filters through sysfs hwtracing: hisi_ptt: Add support for dynamically updating the filter list hwtracing: hisi_ptt: Factor out filter allocation and release operation samples: pfsm: add CC_CAN_LINK dependency misc: fastrpc: check return value of devm_kasprintf() coresight: dummy: Update type of mode parameter in dummy_{sink,source}_enable() ...
| * | | | clk: qcom: cbf-msm8996: scale CBF clock according to the CPUfreqDmitry Baryshkov2023-06-102-1/+60
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Turn CBF into the interconnect provider. Scale CBF frequency (bandwidth) according to CPU frequencies. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Yassine Oudjana <y.oudjana@protonmail.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230512001334.2983048-4-dmitry.baryshkov@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
* | | | Merge tag 'soc-arm-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2023-06-292-1/+4
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC updates from Arnd Bergmann: "These are mostly minor cleanups and bugfixes that address harmless problems. The largest branch is a conversion of the omap platform to use GPIO descriptors throughout the tree, for any devices that are not fully converted to devicetree. The Samsung Exynos platform gains back support for the Exynos4212 chip that was previously unused and removed but is now used for the Samsung Galaxy Tab3" * tag 'soc-arm-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits) ARM: omap2: Fix copy/paste bug MAINTAINERS: Replace my email address Input: ads7846 - fix pointer cast warning Input: ads7846 - Fix usage of match data ARM: omap2: Fix checkpatch issues arm: omap1: replace printk() with pr_err macro ARM: omap: Fix checkpatch issues ARM: s3c: Switch i2c drivers back to use .probe() ARM: versatile: mark mmc_status() static ARM: spear: include "pl080.h" for pl080_get_signal() prototype ARM: sa1100: address missing prototype warnings ARM: pxa: fix missing-prototypes warnings ARM: orion5x: fix d2net gpio initialization ARM: omap2: fix missing tick_broadcast() prototype ARM: omap1: add missing include ARM: lpc32xx: add missing include ARM: imx: add missing include ARM: highbank: add missing include ARM: ep93xx: fix missing-prototype warnings ARM: davinci: fix davinci_cpufreq_init() declaration ...
| * | | | ARM: pxa: fix missing-prototypes warningsArnd Bergmann2023-05-262-1/+4
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PXA platform has a number of configurations that end up with a warning like these when building with W=1: drivers/hwmon/max1111.c:83:5: error: no previous prototype for 'max1111_read_channel' [-Werror=missing-prototypes] arch/arm/mach-pxa/reset.c:86:6: error: no previous prototype for 'pxa_restart' [-Werror=missing-prototypes] arch/arm/mach-pxa/mfp-pxa2xx.c:254:5: error: no previous prototype for 'keypad_set_wake' [-Werror=missing-prototypes] drivers/clk/pxa/clk-pxa25x.c:70:14: error: no previous prototype for 'pxa25x_get_clk_frequency_khz' [-Werror=missing-prototypes] drivers/clk/pxa/clk-pxa25x.c:325:12: error: no previous prototype for 'pxa25x_clocks_init' [-Werror=missing-prototypes] drivers/clk/pxa/clk-pxa27x.c:74:14: error: no previous prototype for 'pxa27x_get_clk_frequency_khz' [-Werror=missing-prototypes] drivers/clk/pxa/clk-pxa27x.c:102:6: error: no previous prototype for 'pxa27x_is_ppll_disabled' [-Werror=missing-prototypes] drivers/clk/pxa/clk-pxa27x.c:470:12: error: no previous prototype for 'pxa27x_clocks_init' [-Werror=missing-prototypes] arch/arm/mach-pxa/pxa27x.c:44:6: error: no previous prototype for 'pxa27x_clear_otgph' [-Werror=missing-prototypes] arch/arm/mach-pxa/pxa27x.c:58:6: error: no previous prototype for 'pxa27x_configure_ac97reset' [-Werror=missing-prototypes] arch/arm/mach-pxa/spitz_pm.c:170:15: error: no previous prototype for 'spitzpm_read_devdata' [-Werror=missing-prototypes] The problem is that there is a declaration for each of these, but it's only seen by the caller and not the callee. Moving these into appropriate header files ensures that both use the same calling conventions and it avoids the warnings. Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230516153109.514251-11-arnd@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | Merge tag 'soc-newsoc-6.5' of ↵Linus Torvalds2023-06-298-0/+1594
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull new ARM SoC support from Arnd Bergmann: "There are two new SoC families this time, and both appear fairly similar: The Nuvoton MA35D1 and the STMicroelectronics STM32MP2 are both dual-core Cortex-A35 based chips for the low-power industrial embedded market, and they mark the first 64-bit product in a widely used family of 32-bit Arm MCUs and SoCs. The way into the kernel is completely different here: The team at ST has a long history of working upstream with their STM32MP1 and other SoCs, and they produced a complete port to arm64 together with the initial announcement. Nuvoton also has multiple SoC product lines with current or previous upstream support, but those are maintained by third parties and are unrelated. The patch series from Nuvoton's Jacky Huang had to go through many revisisions to get to this point and is still missing a few drivers including the serial port for the moment. The branch contains the devicetree files as well as all the code changes, in order to have something that can be tested standalone" * tag 'soc-newsoc-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits) clk: nuvoton: Use clk_parent_data instead of string for parent clock clk: nuvoton: Update all constant hex values to lowercase clk: nuvoton: Add clk-ma35d1.h for driver extern functions remoteproc: stm32: use correct format strings on 64-bit MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE arm64: defconfig: enable ARCH_STM32 and STM32 serial driver arm64: dts: st: add stm32mp257f-ev1 board support dt-bindings: stm32: document stm32mp257f-ev1 board arm64: dts: st: introduce stm32mp25 pinctrl files arm64: dts: st: introduce stm32mp25 SoCs family arm64: introduce STM32 family on Armv8 architecture dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon pinctrl: stm32: add stm32mp257 pinctrl support dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages Documentation/process: add soc maintainer handbook reset: RESET_NUVOTON_MA35D1 should depend on ARCH_MA35 reset: Add Nuvoton ma35d1 reset driver support clk: nuvoton: Add clock driver for ma35d1 clock controller arm64: dts: nuvoton: Add initial ma35d1 device tree dt-bindings: serial: Document ma35d1 uart controller ...
| * | | | clk: nuvoton: Use clk_parent_data instead of string for parent clockJacky Huang2023-06-221-87/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the declaration of parent clocks, use struct clk_parent_data instead of a string. Due to the change in the passed arguments, replace the usage of devm_clk_hw_register_mux() with clk_hw_register_mux_parent_data() for all cases. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | | clk: nuvoton: Update all constant hex values to lowercaseJacky Huang2023-06-221-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The constant hex values used to define register offsets were written in uppercase. This patch update all these constant hex values to be lowercase. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | | clk: nuvoton: Add clk-ma35d1.h for driver extern functionsJacky Huang2023-06-224-16/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the declaration of extern functions ma35d1_reg_clk_pll() and ma35d1_reg_adc_clkdiv() from the .c files to the newly created header file clk-ma35d1.h. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | | clk: nuvoton: Add clock driver for ma35d1 clock controllerJacky Huang2023-06-057-0/+1454
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. This driver support ma35d1 clock gating, divider, and individual PLL configuration. There are 6 PLLs in ma35d1 SoC: - CA-PLL for the two Cortex-A35 CPU clock - SYS-PLL for system bus, which comes from the companion MCU and cannot be programmed by clock controller. - DDR-PLL for DDR - EPLL for GMAC and GFX, Display, and VDEC IPs. - VPLL for video output pixel clock - APLL for SDHC, I2S audio, and other IPs. CA-PLL has only one operation mode. DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3 operation modes: integer mode, fraction mode, and spread specturm mode. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | Merge tag 'mips_6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds2023-06-293-0/+1125
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Thomas Bogendoerfer: - add support for TP-Link HC220 G5 v1 - add support for Wifi/Bluetooth on CI20 - rework Ralink clock and reset handling - cleanups and fixes * tag 'mips_6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (58 commits) MIPS: Loongson64: DTS: Add RTC support to Loongson-2K1000 MIPS: Loongson64: DTS: Add RTC support to LS7A PCH MIPS: OCTEON: octeon-usb: cleanup divider calculation MIPS: OCTEON: octeon-usb: introduce dwc3_octeon_{read,write}q MIPS: OCTEON: octeon-usb: move gpio config to separate function MIPS: OCTEON: octeon-usb: use bitfields for shim register MIPS: OCTEON: octeon-usb: use bitfields for host config register MIPS: OCTEON: octeon-usb: use bitfields for control register MIPS: OCTEON: octeon-usb: add all register offsets mips: ralink: match all supported system controller compatible strings MIPS: dec: prom: Address -Warray-bounds warning MIPS: DTS: CI20: Raise VDDCORE voltage to 1.125 volts clk: ralink: mtmips: Fix uninitialized use of ret in mtmips_register_{fixed,factor}_clocks() mips: ralink: introduce commonly used remap node function mips: pci-mt7620: use dev_info() to log PCIe device detection result mips: pci-mt7620: do not print NFTS register value as error log MAINTAINERS: add Mediatek MTMIPS Clock maintainer mips: ralink: get cpu rate from new driver code mips: ralink: remove reset related code mips: ralink: mt7620: remove clock related code ...
| * | | | clk: ralink: mtmips: Fix uninitialized use of ret in ↵Nathan Chancellor2023-06-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mtmips_register_{fixed,factor}_clocks() Clang warns: drivers/clk/ralink/clk-mtmips.c:309:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized] 309 | return ret; | ^~~ drivers/clk/ralink/clk-mtmips.c:285:9: note: initialize the variable 'ret' to silence this warning 285 | int ret, i; | ^ | = 0 drivers/clk/ralink/clk-mtmips.c:359:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized] 359 | return ret; | ^~~ drivers/clk/ralink/clk-mtmips.c:335:9: note: initialize the variable 'ret' to silence this warning 335 | int ret, i; | ^ | = 0 2 errors generated. Set ret to the return value of clk_hw_register_fixed_rate() using the PTR_ERR() macro, which ensures ret is not used uninitialized, clearing up the warning. Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs") Closes: https://github.com/ClangBuiltLinux/linux/issues/1879 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * | | | clk: ralink: add clock and reset driver for MTMIPS SoCsSergio Paracuellos2023-06-213-0/+1123
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, clock related code for old ralink SoCs was based in fixed clocks using 'clk_register_fixed_rate' and 'clkdev_create' directly doing in code and not using device tree at all for their definition. Including this driver is an effort to be able to define proper clocks using device tree and also cleaning all the clock and reset related code from 'arch/mips/ralink' dir. This clock and reset driver covers all the ralink SoCs but MT7621 which is the newest and provides gating and some differences that make it different from its predecesors. It has its own driver since some time ago. The ralink SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883, RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver has been extracted from 'arch/mips/ralink' and cleanly put using kernel clock driver APIs. The clock plans for this SoCs only talks about relation between CPU frequency and BUS frequency. This relation is different depending on the particular SoC. CPU clock is derived from XTAL frequencies. Depending on the SoC we have the following frequencies: * RT2880 SoC: - XTAL: 40 MHz. - CPU: 250, 266, 280 or 300 MHz. - BUS: CPU / 2 MHz. * RT3050, RT3052, RT3350: - XTAL: 40 MHz. - CPU: 320 or 384 MHz. - BUS: CPU / 3 MHz. * RT3352: - XTAL: 40 MHz. - CPU: 384 or 400 MHz. - BUS: CPU / 3 MHz. - PERIPH: 40 MHz. * RT3383: - XTAL: 40 MHz. - CPU: 250, 384, 480 or 500 MHz. - BUS: Depends on RAM Type and CPU: + RAM DDR2: 125. ELSE 83 MHz. + RAM DDR2: 128. ELSE 96 MHz. + RAM DDR2: 160. ELSE 120 MHz. + RAM DDR2: 166. ELSE 125 MHz. * RT5350: - XTAL: 40 MHz. - CPU: 300, 320 or 360 MHz. - BUS: CPU / 3, CPU / 4, CPU / 3 MHz. - PERIPH: 40 MHz. * MT7628 and MT7688: - XTAL: 20 MHz or 40 MHz. - CPU: 575 or 580 MHz. - BUS: CPU / 3. - PCMI2S: 480 MHz. - PERIPH: 40 MHz. * MT7620: - XTAL: 20 MHz or 40 MHz. - PLL: XTAL, 480, 600 MHz. - CPU: depends on PLL and some mult and dividers. - BUS: depends on PLL and some mult and dividers. - PERIPH: 40 or XTAL MHz. MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of register reads and predividers. To derive CPU and BUS frequencies in the MT7620 SoC 'mt7620_calc_rate()' helper is used. In the case XTAL can have different frequencies and we need a different clock frequency for peripherals 'periph' clock in introduced. The rest of the peripherals present in the SoC just follow their parent frequencies. With this information the clk driver will provide all the clock and reset functionality from a set of hardcoded clocks allowing to define a nice device tree without fixed clocks. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* | | | Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-06-29251-753/+4046
|\ \ \ \ | | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This batch of clk driver updates contains almost no new SoC support. Instead there's a treewide patch series from Maxime that makes clk_ops::determine_rate mandatory for muxes. Beyond that core framework change we have the usual pile of clk driver updates such as migrating i2c drivers to use .probe() again or YAMLfication of clk DT bindings so we can validate DTBs. Overall the SoCs that got the most updates this time around in terms of diffstat are the Amlogic and Mediatek drivers because they added new SoC support or fixed up various drivers to have proper data. In general things look kinda quiet. I suspect the core framework change may still shake out some problems after the merge window, mostly because not everyone tests linux-next where that series has been for some number of weeks. I saw that there's at least one pending fix for Tegra that needs to be wrapped up into a proper patch. I'll try to catch those bits before the window closes so that -rc1 is bootable. More details below. Core: - Make clk_ops::determine_rate mandatory for muxes New Drivers: - Add amlogic a1 SoC family PLL and peripheral clock controller support Updates: - Handle allocation failures from kasprintf() and friends - Migrate platform clk drivers to .remove_new() - Migrate i2c clk drivers to .probe() instead of .probe_new() - Remove CLK_SET_PARENT from all Mediatek MSDC core clocks - Add infra_ao reset support for Mediatek MT8188 SoCs - Align driver_data to i2c_device_id tables in some i2c clk drivers - Use device_get_match_data() in vc5 clk driver - New Kconfig symbol name (SOC_MICROCHIP_POLARFIRE) for Microchip FPGA clock drivers - Use of_property_read_bool() to read "microchip,pic32mzda-sosc" boolean DT property in clk-pic32mzda - Convert AT91 clock dt-bindings to YAML - Remove CLK_SET_RATE_PARENT flag from LDB clocks on i.MX6SX - Keep i.MX UART clocks enabled during kernel boot if earlycon is set - Drop imx_unregister_clocks() as there are no users anymore - Switch to _safe iterator on imx_clk_scu_unregister() to avoid use after free - Add determine_rate op to the imx8m composite clock - Use device managed API for iomap and kzalloc for i.MXRT1050, i.MX8MN, i.MX8MP and i.MX93 clock controller drivers - Add missing interrupt DT property for the i.MX8M clock controller - Re-add support for Exynos4212 clock controller because we are re-introducing the SoC in the mainline - Add CONFIG_OF dependency to Samsung clk Kconfig symbols to solve some objtool warnings - Preselect PLL MIPI as TCON0 parent for Allwinner A64 SoC - Convert the Renesas clock drivers to readl_poll_timeout_atomic() - Add PWM clock on Renesas R-Car V3U - Fix PLL5 on Renesas RZ/G2L and RZ/V2L" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (149 commits) clk: fix typo in clk_hw_register_fixed_rate_parent_data() macro clk: Fix memory leak in devm_clk_notifier_register() clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes clk: mvebu: Use of_get_cpu_hwid() to read CPU ID MAINTAINERS: Add Marvell mvebu clock drivers clk: clocking-wizard: check return value of devm_kasprintf() clk: ti: clkctrl: check return value of kasprintf() clk: keystone: sci-clk: check return value of kasprintf() clk: si5341: free unused memory on probe failure clk: si5341: check return value of {devm_}kasprintf() clk: si5341: return error if one synth clock registration fails clk: cdce925: check return value of kasprintf() clk: vc5: check memory returned by kasprintf() clk: mediatek: clk-mt8173-apmixedsys: Fix iomap not released issue clk: mediatek: clk-mt8173-apmixedsys: Fix return value for of_iomap() error clk: mediatek: clk-mtk: Grab iomem pointer for divider clocks clk: keystone: syscon-clk: Add support for audio refclk dt-bindings: clock: Add binding documentation for TI Audio REFCLK dt-bindings: clock: ehrpwm: Remove unneeded syscon compatible clk: keystone: syscon-clk: Allow the clock node to not be of type syscon ...
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| *---------. \ \ Merge branches 'clk-imx', 'clk-microchip', 'clk-cleanup', 'clk-bindings', ↵Stephen Boyd2023-06-2626-99/+223
| |\ \ \ \ \ \ \ \ | | | | | | |_|/ / | | | | | |/| | / | | | | |_|_|_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-ti' and 'clk-kasprintf' into clk-next - Handle allocation failures from kasprintf() and friends * clk-imx: clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe() clk: imx93: fix memory leak and missing unwind goto in imx93_clocks_probe clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probe dt-bindings: clock: imx8m: Add missing interrupt property clk: imx: clk-imxrt1050: fix memory leak in imxrt1050_clocks_probe clk: imx: composite-8m: Add imx8m_divider_determine_rate clk: imx: scu: use _safe list iterator to avoid a use after free clk: imx: drop imx_unregister_clocks clk: imx6ul: retain early UART clocks during kernel init clk: imx: imx6sx: Remove CLK_SET_RATE_PARENT from the LDB clocks * clk-microchip: dt-bindings: clocks: at91sam9x5-sckc: convert to yaml dt-bindings: clocks: atmel,at91rm9200-pmc: convert to yaml clk: microchip: Use of_property_read_bool() for boolean properties clk: microchip: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE * clk-cleanup: clk: fix typo in clk_hw_register_fixed_rate_parent_data() macro clk: Fix memory leak in devm_clk_notifier_register() clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes clk: mvebu: Use of_get_cpu_hwid() to read CPU ID MAINTAINERS: Add Marvell mvebu clock drivers clk: mvebu: Use of_address_to_resource() clk: tegra: tegra124-emc: Fix potential memory leak clk: clocking-wizard: Fix Oops in clk_wzrd_register_divider() clk: bcm: rpi: Fix off by one in raspberrypi_discover_clocks() clk: sifive: Use devm_platform_ioremap_resource() * clk-bindings: dt-bindings: clock: drop unneeded quotes and use absolute /schemas path dt-bindings: rcc: stm32: Sync with u-boot copy for STM32MP13 SoC * clk-ti: clk: keystone: syscon-clk: Add support for audio refclk dt-bindings: clock: Add binding documentation for TI Audio REFCLK dt-bindings: clock: ehrpwm: Remove unneeded syscon compatible clk: keystone: syscon-clk: Allow the clock node to not be of type syscon * clk-kasprintf: clk: clocking-wizard: check return value of devm_kasprintf() clk: ti: clkctrl: check return value of kasprintf() clk: keystone: sci-clk: check return value of kasprintf() clk: si5341: free unused memory on probe failure clk: si5341: check return value of {devm_}kasprintf() clk: si5341: return error if one synth clock registration fails clk: cdce925: check return value of kasprintf() clk: vc5: check memory returned by kasprintf()
| | | | | | | * clk: clocking-wizard: check return value of devm_kasprintf()Claudiu Beznea2023-06-161-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 2046338dcbc6 ("ARM: mxs: Use soc bus infrastructure") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-9-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | | * clk: ti: clkctrl: check return value of kasprintf()Claudiu Beznea2023-06-161-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 852049594b9a ("clk: ti: clkctrl: convert subclocks to use proper names also") Fixes: 6c3090520554 ("clk: ti: clkctrl: Fix hidden dependency to node name") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-8-claudiu.beznea@microchip.com Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | | * clk: keystone: sci-clk: check return value of kasprintf()Claudiu Beznea2023-06-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support") Depends-on: 96488c09b0f4 ("clk: keystone: sci-clk: cut down the clock name length") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-7-claudiu.beznea@microchip.com Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | | * clk: si5341: free unused memory on probe failureClaudiu Beznea2023-06-161-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pointers from synth_clock_names[] should be freed at the end of probe either on probe success or failure path. Fixes: b7bbf6ec4940 ("clk: si5341: Allow different output VDD_SEL values") Fixes: 9b13ff4340df ("clk: si5341: Add sysfs properties to allow checking/resetting device faults") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-6-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | | * clk: si5341: check return value of {devm_}kasprintf()Claudiu Beznea2023-06-161-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | {devm_}kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 3044a860fd09 ("clk: Add Si5341/Si5340 driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-5-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | | * clk: si5341: return error if one synth clock registration failsClaudiu Beznea2023-06-161-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case devm_clk_hw_register() fails for one of synth clocks the probe continues. Later on, when registering output clocks which have as parents all the synth clocks, in case there is registration failure for at least one synth clock the information passed to clk core for registering output clock is not right: init.num_parents is fixed but init.parents may contain an array with less parents. Fixes: 3044a860fd09 ("clk: Add Si5341/Si5340 driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-4-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | | * clk: cdce925: check return value of kasprintf()Claudiu Beznea2023-06-161-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 19fbbbbcd3a3 ("Add TI CDCE925 I2C controlled clock synthesizer driver") Depends-on: e665f029a283 ("clk: Convert to using %pOFn instead of device_node.name") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-3-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | | * clk: vc5: check memory returned by kasprintf()Claudiu Beznea2023-06-161-0/+29
| | | | | | |/ | | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: f491276a5168 ("clk: vc5: Allow Versaclock driver to support multiple instances") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-2-claudiu.beznea@microchip.com Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * clk: keystone: syscon-clk: Add support for audio refclkJai Luthra2023-06-161-5/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI's AM62 SoC can optionally provide two audio reference clocks (AUDIO_REFCLKx) to external peripherals. By default this reference clock is looped-back inside the SoC to a mux that goes to McASP AHCLK, but can optionally be enabled as an output to peripherals outside the SoC by setting a bit through CTRL_MMR registers. This bit only controls the direction of the clock, while the parent is a muxed input from sci-clk [1] which may be a configurable PLL or a master clock from one of the McASP instances. Link: http://downloads.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#clocks-for-board0-device [1] Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20230515-refclk-v3-2-37c0b550f406@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * clk: keystone: syscon-clk: Allow the clock node to not be of type sysconAndrew Davis2023-06-161-2/+2
| | | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a helper device_node_to_regmap() we can use that does not force this clock DT node to be a "syscon" node. It should work the same in this case but allow us to remove the unneeded "syscon" compatible. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230516184626.154892-1-afd@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | clk: Fix memory leak in devm_clk_notifier_register()Fei Shao2023-06-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_clk_notifier_register() allocates a devres resource for clk notifier but didn't register that to the device, so the notifier didn't get unregistered on device detach and the allocated resource was leaked. Fix the issue by registering the resource through devres_add(). This issue was found with kmemleak on a Chromebook. Fixes: 6d30d50d037d ("clk: add devm variant of clk_notifier_register") Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20230619112253.v2.1.I13f060c10549ef181603e921291bdea95f83033c@changeid Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | clk: mvebu: Iterate over possible CPUs instead of DT CPU nodesRob Herring2023-06-201-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework iterating over DT CPU nodes to iterate over possible CPUs instead. There's no need to walk the DT CPU nodes again. Possible CPUs is equal to the number of CPUs defined in the DT. Using the "reg" value for an array index is fragile as it assumes "reg" is 0-N which often is not the case. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230327-mvebu-clk-fixes-v2-3-8333729ee45d@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | clk: mvebu: Use of_get_cpu_hwid() to read CPU IDRob Herring2023-06-201-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use of_get_cpu_hwid() rather than the open coded reading of the CPU nodes "reg" property. The existing code is in fact wrong as the "reg" address cells size is 2 cells for arm64. The existing code happens to work because the DTS files are wrong as well. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230327-mvebu-clk-fixes-v2-2-8333729ee45d@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | clk: mvebu: Use of_address_to_resource()Rob Herring2023-06-141-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace of_get_property() and of_translate_address() calls with a single call to of_address_to_resource(). Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230406010738.1269781-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | clk: tegra: tegra124-emc: Fix potential memory leakYuan Can2023-06-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tegra and tegra needs to be freed in the error handling path, otherwise it will be leaked. Fixes: 2db04f16b589 ("clk: tegra: Add EMC clock driver") Signed-off-by: Yuan Can <yuancan@huawei.com> Link: https://lore.kernel.org/r/20221209094124.71043-1-yuancan@huawei.com Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | clk: clocking-wizard: Fix Oops in clk_wzrd_register_divider()Dan Carpenter2023-06-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Smatch detected this potential error pointer dereference clk_wzrd_register_divider(). If devm_clk_hw_register() fails then it sets "hw" to an error pointer and then dereferences it on the next line. Return the error directly instead. Fixes: 5a853722eb32 ("staging: clocking-wizard: Add support for dynamic reconfiguration") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/f0e39b5c-4554-41e0-80d9-54ca3fabd060@kili.mountain Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | clk: bcm: rpi: Fix off by one in raspberrypi_discover_clocks()Dan Carpenter2023-06-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Smatch detected an off by one in this code: drivers/clk/bcm/clk-raspberrypi.c:374 raspberrypi_discover_clocks() error: buffer overflow 'data->hws' 16 <= 16 The data->hws[] array has RPI_FIRMWARE_NUM_CLK_ID elements so the > comparison needs to changed to >=. Fixes: 12c90f3f27bb ("clk: bcm: rpi: Add variant structure") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/5a850b08-d2f5-4794-aceb-a6b468965139@kili.mountain Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | clk: sifive: Use devm_platform_ioremap_resource()Yang Li2023-06-141-3/+1
| | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert platform_get_resource(),devm_ioremap_resource() to a single call to devm_platform_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20230428070005.41192-1-yang.lee@linux.alibaba.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * | clk: microchip: Use of_property_read_bool() for boolean propertiesRob Herring2023-05-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to to of_property_read_bool(). Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230310144701.1541573-1-robh@kernel.org
| | | * | clk: microchip: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIREConor Dooley2023-05-221-2/+2
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the use of such symbols on other architectures, convert the Microchip FPGA clock drivers to use the new symbol. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230309204452.969574-2-conor@kernel.org
| | * | clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe()Yuxing Liu2023-06-121-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace of_iomap() and kzalloc() with devm_of_iomap() and devm_kzalloc() which can automatically release the related memory when the device or driver is removed or unloaded to avoid potential memory leak. In this case, iounmap(anatop_base) in line 427,433 are removed as manual release is not required. Besides, referring to clk-imx8mq.c, check the return code of of_clk_add_hw_provider, if it returns negtive, print error info and unregister hws, which makes the program more robust. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Yuxing Liu <lyx2022@hust.edu.cn> Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230503070607.2462-1-lyx2022@hust.edu.cn Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-08 01:22:31 +0000