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* clk: sunxi: a31: Export the MIPI PLLMaxime Ripard2020-01-041-1/+3
* clk: sunxi-ng: a64: export CLK_CPUX clock for DVFSVasily Khoruzhick2020-01-041-1/+0
* clk: sunxi-ng: add mux and pll notifiers for A64 CPU clockIcenowy Zheng2020-01-041-1/+27
* clk: sunxi-ng: r40: Export MBUS clockChen-Yu Tsai2020-01-031-4/+0
* clk: sunxi: use of_device_get_match_dataCorentin Labbe2019-12-091-4/+2
* Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2019-12-052-1/+6
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| * Merge tag 'mmp-soc-for-v5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/g...Olof Johansson2019-10-212-1/+6
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| | * ARM: mmp: add support for MMP3 SoCLubomir Rintel2019-10-172-1/+6
* | | Merge branch 'thermal/next' of git://git.kernel.org/pub/scm/linux/kernel/git/...Linus Torvalds2019-12-053-3/+3
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| * | | clk: qcom: Initialize clock drivers earlierAmit Kucheria2019-11-073-3/+3
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* | | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-12-01115-2241/+7936
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| *-----. \ \ Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...Stephen Boyd2019-11-2712-10/+1284
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| | | | | * | clk: Add common clock driver for BM1880 SoCManivannan Sadhasivam2019-11-223-0/+977
| | | | | * | clk: Add clk_hw_unregister_composite helper function definitionManivannan Sadhasivam2019-11-221-0/+11
| | | | | * | clk: Zero init clk_init_data in helpersManivannan Sadhasivam2019-11-225-5/+5
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| | | * | | clk: mark clk_disable_unused() as __initRasmus Villemoes2019-11-191-4/+4
| | | * | | clk: Fix memory leak in clk_unregister()Kishon Vijay Abraham I2019-11-191-0/+1
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| | * | | clk: ingenic: Allow drivers to be built with COMPILE_TESTStephen Boyd2019-11-221-1/+1
| | * | | clk: Ingenic: Add CGU driver for X1000.Zhou Yanjie2019-11-133-0/+285
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| *-------. \ \ Merge branches 'clk-gpio-flags', 'clk-tegra', 'clk-rockchip', 'clk-sprd' and ...Stephen Boyd2019-11-2728-210/+1031
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| | | | | | * | | clk: pxa: fix one of the pxa RTC clocksRobert Jarzmik2019-11-131-0/+1
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| | | | | * / / clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_...Baolin Wang2019-11-131-1/+1
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| | | | * | | clk: rockchip: protect the pclk_usb_grf as critical on px30Heiko Stuebner2019-11-051-1/+2
| | | | * | | clk: rockchip: add video-related niu clocks as critical on px30Heiko Stuebner2019-11-051-5/+10
| | | | * | | clk: rockchip: move px30 critical clocks to correct clock controllerHeiko Stuebner2019-11-051-4/+4
| | | | * | | clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandcFinley Xiao2019-11-051-4/+40
| | | | * | | clk: rockchip: make clk_half_divider_ops staticBen Dooks (Codethink)2019-10-311-2/+1
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| | | * | | clk: tegra: Use match_string() helper to simplify the codeYueHaibing2019-11-131-8/+4
| | | * | | clk: tegra: Fix build error without CONFIG_PM_SLEEPYueHaibing2019-11-111-0/+2
| | | * | | clk: tegra: Optimize PLLX restore on Tegra20/30Dmitry Osipenko2019-11-112-18/+32
| | | * | | clk: tegra: Add suspend and resume support on Tegra210Sowjanya Komatineni2019-11-113-4/+163
| | | * | | clk: tegra: Share clk and rst register defines with Tegra clock driverSowjanya Komatineni2019-11-112-45/+45
| | | * | | clk: tegra: Use fence_udelay() during PLLU initSowjanya Komatineni2019-11-111-4/+4
| | | * | | clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni2019-11-113-0/+59
| | | * | | clk: tegra: clk-super: Add restore-context supportSowjanya Komatineni2019-11-111-0/+27
| | | * | | clk: tegra: clk-super: Fix to enable PLLP branches to CPUSowjanya Komatineni2019-11-114-1/+39
| | | * | | clk: tegra: periph: Add restore_context supportSowjanya Komatineni2019-11-112-0/+37
| | | * | | clk: tegra: Support for OSC context save and restoreSowjanya Komatineni2019-11-112-0/+16
| | | * | | clk: tegra: pll: Save and restore pll contextSowjanya Komatineni2019-11-111-32/+54
| | | * | | clk: tegra: pllout: Save and restore pllout contextSowjanya Komatineni2019-11-111-0/+9
| | | * | | clk: tegra: divider: Save and restore divider rateSowjanya Komatineni2019-11-111-0/+11
| | | * | | clk: tegra: Reimplement SOR clocks on Tegra210Thierry Reding2019-11-111-16/+55
| | | * | | clk: tegra: Reimplement SOR clock on Tegra124Thierry Reding2019-11-111-9/+13
| | | * | | clk: tegra: Rename sor0_lvds to sor0_outThierry Reding2019-11-113-8/+8
| | | * | | clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding2019-11-112-8/+49
| | | * | | clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRCThierry Reding2019-11-112-2/+2
| | | * | | Merge branch 'for-5.5/clk-core' into for-5.5/clkThierry Reding2019-11-111-0/+18
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| | | | * | | clk: Add API to get index of the clock parentSowjanya Komatineni2019-11-111-0/+18
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| | | * / / clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko2019-11-115-52/+339
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| | * / / clk: clk-gpio: propagate rate change to parentMichael Hennerich2019-11-081-1/+1
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