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* clk: tegra30: Add hda clock default rates to clock driverPeter Geis2021-01-121-0/+2
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-12-2199-1380/+8252
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| *-------. Merge branches 'clk-ingenic', 'clk-vc5', 'clk-cleanup', 'clk-canaan' and 'clk...Stephen Boyd2020-12-207-10/+19
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| | | | | | * clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9Terry Zhou2020-12-191-2/+2
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| | | | * | clk: sunxi-ng: Make sure divider tables have sentinelJernej Skrabec2020-12-192-0/+2
| | | | * | clk: s2mps11: Fix a resource leak in error handling paths in the probe functionChristophe JAILLET2020-12-191-0/+1
| | | | * | clk: bcm: dvp: Add MODULE_DEVICE_TABLE()Nicolas Saenz Julienne2020-12-191-0/+1
| | | | * | clk: bcm: dvp: drop a variable that is assigned to onlyUwe Kleine-König2020-12-191-2/+1
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| | | * / clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"Geert Uytterhoeven2020-12-191-2/+2
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| | * / clk: ingenic: Fix divider calculation with div tablesPaul Cercueil2020-12-191-4/+10
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| *-------. \ Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and 'clk-silab...Stephen Boyd2020-12-2020-280/+905
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| | | | | | * | clk: si5351: Wait for bit clear after PLL resetSascha Hauer2020-12-191-3/+10
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| | | | | * | clk: at91: sam9x60: remove atmel,osc-bypass supportAlexandre Belloni2020-12-191-5/+1
| | | | | * | clk: at91: sama7g5: register cpu clockClaudiu Beznea2020-12-191-7/+6
| | | | | * | clk: at91: clk-master: re-factor master clockClaudiu Beznea2020-12-1914-146/+542
| | | | | * | clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHzClaudiu Beznea2020-12-191-14/+47
| | | | | * | clk: at91: sama7g5: decrease lower limit for MCK0 rateClaudiu Beznea2020-12-191-1/+1
| | | | | * | clk: at91: sama7g5: remove mck0 from parent list of other clocksClaudiu Beznea2020-12-191-29/+26
| | | | | * | clk: at91: clk-sam9x60-pll: allow runtime changes for pllClaudiu Beznea2020-12-194-41/+197
| | | | | * | clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev2020-12-191-2/+2
| | | | | * | clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev2020-12-192-2/+2
| | | | | * | clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DTEugen Hristev2020-12-191-2/+4
| | | | | * | dt-bindings: clock: at91: add sama7g5 pll definesEugen Hristev2020-12-191-3/+3
| | | | | * | clk: at91: sama7g5: fix compilation errorClaudiu Beznea2020-12-191-2/+4
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| | | | * / clk: Trace clk_set_rate() "range" functionsMaxime Ripard2020-12-171-0/+6
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| | | * | clk: axi-clkgen: move the OF table at the bottom of the fileAlexandru Ardelean2020-12-171-9/+9
| | | * | clk: axi-clkgen: wrap limits in a struct and keep copy on the state objectAlexandru Ardelean2020-12-171-17/+31
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| | * | clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERsDavid Shah2020-12-171-1/+11
| | * | clk: ti: Fix memleak in ti_fapll_synth_setupZhang Qilong2020-12-171-2/+9
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| *-------. \ Merge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and 'clk-...Stephen Boyd2020-12-2027-726/+1673
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| | | | | | * | clk: Add hardware-enable column to clk summaryDmitry Osipenko2020-12-171-4/+11
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| | | | | * / clk: mediatek: Make mtk_clk_register_mux() a static functionWeiyi Lu2020-12-172-5/+1
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| | | | * | clk: sifive: Add clock enable and disable opsPragnesh Patel2020-12-164-9/+93
| | | | * | clk: sifive: Fix the wrong bit field shiftZong Li2020-12-161-2/+2
| | | | * | clk: sifive: Add a driver for the SiFive FU740 PRCI IP blockZong Li2020-12-166-3/+346
| | | | * | clk: sifive: Use common name for prci configurationZong Li2020-12-162-4/+4
| | | | * | clk: sifive: Extract prci core to common baseZong Li2020-12-165-571/+641
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| | | * | clk: imx: scu: remove the calling of device_is_boundDong Aisheng2020-11-301-11/+4
| | | * | clk: imx: scu: Make pd_np with static keywordZou Wei2020-11-101-1/+1
| | | * | clk: imx8mq: drop of_match_ptr from of_device_id tableKrzysztof Kozlowski2020-11-101-1/+1
| | | * | clk: imx8mp: drop of_match_ptr from of_device_id tableKrzysztof Kozlowski2020-11-101-1/+1
| | | * | clk: imx8mn: drop of_match_ptr from of_device_id tableKrzysztof Kozlowski2020-11-101-1/+1
| | | * | clk: imx8mm: drop of_match_ptr from of_device_id tableKrzysztof Kozlowski2020-11-101-1/+1
| | | * | clk: imx: gate2: Remove unused variable retZou Wei2020-11-101-2/+1
| | | * | clk: imx: gate2: Add locking in is_enabled opAbel Vesa2020-11-031-1/+9
| | | * | clk: imx: gate2: Add cgr_mask for more flexible number of control bitsAbel Vesa2020-11-032-18/+22
| | | * | clk: imx: gate2: Check if clock is enabled against cgr_valAbel Vesa2020-11-031-3/+3
| | | * | clk: imx: gate2: Keep the register writing in on placeAbel Vesa2020-11-031-17/+16
| | | * | clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special caseAbel Vesa2020-11-032-25/+8
| | | * | clk: imx: scu: fix build break when compiled as modulesDong Aisheng2020-11-031-2/+2
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