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path: root/drivers/clocksource/timer-riscv.c
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* clocksource/timer-riscv: Add riscv_clock_shutdown callbackJoshua Yeong2023-12-271-0/+7
* Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-101-1/+1
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| * riscv: Rearrange hwcap.h and cpufeature.hXiao Wang2023-11-091-1/+1
* | Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-081-2/+15
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| * clocksource: timer-riscv: Increase rating of clock_event_device for SstcAnup Patel2023-10-311-0/+2
| * clocksource: timer-riscv: Don't enable/disable timer interruptAnup Patel2023-10-311-2/+13
* | clocksource/timer-riscv: ACPI: Add timer_cannot_wakeup_cpuSunil V L2023-10-111-0/+4
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* clocksource/timer-riscv: Add ACPI supportSunil V L2023-06-011-0/+11
* clocksource/timer-riscv: Refactor riscv_timer_init_dt()Sunil V L2023-06-011-41/+40
* clocksource/drivers/riscv: Patch riscv_clock_next_event() jump before first useMatt Evans2023-02-131-5/+5
* clocksource/drivers/riscv: Get rid of clocksource_arch_init() callbackLad Prabhakar2023-02-131-0/+5
* clocksource/drivers/riscv: Increase the clock source ratingSamuel Holland2023-02-131-1/+1
* clocksource/drivers/timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DTAnup Patel2023-02-131-0/+10
* Revert "clocksource/drivers/riscv: Events are stopped during CPU suspend"Conor Dooley2022-12-011-1/+1
* RISC-V: Add Sstc extension supportPalmer Dabbelt2022-08-111-1/+24
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| * RISC-V: Prefer sstc extension if availableAtish Patra2022-08-111-1/+24
* | riscv: cpu: Add 64bit hartid support on RV64Sunil V L2022-07-191-7/+8
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* clocksource/drivers/riscv: Events are stopped during CPU suspendSamuel Holland2022-05-181-1/+1
* RISC-V: KVM: Add timer functionalityAtish Patra2021-10-041-0/+9
* RISC-V: Remove CLINT related code from timer and archAnup Patel2020-08-201-15/+2
* clocksource/drivers/timer-riscv: Use per-CPU timer interruptAnup Patel2020-06-091-3/+40
* clocksource: riscv: add notrace to riscv_sched_clockZong Li2020-01-041-1/+1
* riscv: add support for MMIO access to the timer registersChristoph Hellwig2019-11-131-4/+19
* riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-4/+4
* riscv: don't use the rdtime(h) pseudo-instructionsChristoph Hellwig2019-09-051-13/+4
* RISC-V: Remove per cpu clocksourceAtish Patra2019-08-061-4/+2
* clocksource/drivers/riscv: Fix clocksource maskAtish Patra2019-03-231-3/+2
* clocksource/drivers/riscv: Add required checks during clock source initAtish Patra2019-02-231-3/+20
* clocksource/drivers/riscv: Change name riscv_timer to timer-riscvDaniel Lezcano2018-12-181-0/+118
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