summaryrefslogtreecommitdiffstats
path: root/drivers/cxl/acpi.c
Commit message (Expand)AuthorAgeFilesLines
* cxl/acpi: Minimize granularity for x1 interleavesDan Williams2022-08-011-0/+6
* cxl/acpi: Autoload driver for 'cxl_acpi' test devicesDan Williams2022-08-011-0/+7
* cxl/port: Record parent dport when adding portsDan Williams2022-07-211-2/+1
* cxl/core: Define a 'struct cxl_root_decoder'Dan Williams2022-07-211-4/+36
* cxl/acpi: Track CXL resources in iomem_resourceDan Williams2022-07-211-3/+141
* cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams2022-07-211-1/+3
* cxl: Introduce cxl_to_{ways,granularity}Dan Williams2022-07-091-15/+19
* cxl/core: Drop ->platform_res attribute for root decodersDan Williams2022-07-091-7/+10
* cxl/acpi: Add root device lockdep validationDan Williams2022-04-281-0/+13
* cxl/core/port: Fix / relax decoder target enumerationDan Williams2022-02-081-1/+1
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-081-1/+2
* cxl/core/port: Add switch port enumerationDan Williams2022-02-081-16/+1
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-081-1/+1
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-081-25/+1
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-081-28/+15
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-081-59/+8
* cxl/pci: Rename pci.h to cxlpci.hDan Williams2022-02-081-1/+1
* cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams2022-02-081-0/+2
* cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams2022-02-081-5/+9
* cxl: Prove CXL lockingDan Williams2022-02-081-5/+5
* cxl/core/port: Make passthrough decoder init implicitBen Widawsky2022-02-081-5/+0
* cxl/core/port: Clarify decoder creationBen Widawsky2022-02-081-2/+2
* cxl/core: Convert decoder range to resourceBen Widawsky2022-02-081-14/+8
* cxl/acpi: Map component registers for Root PortsBen Widawsky2022-02-081-2/+11
* ACPI: NUMA: Add a node and memblk for each CFMWS not in SRATAlison Schofield2021-11-151-1/+2
* cxl/test: Mock acpi_table_parse_cedt()Dan Williams2021-11-151-0/+2
* cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpersDan Williams2021-11-151-147/+87
* cxl/acpi: Do not fail cxl_acpi_probe() based on a missing CHBSAlison Schofield2021-10-081-4/+6
* cxl/core: Split decoder setup into alloc + addDan Williams2021-09-211-24/+60
* cxl/bus: Populate the target list at decoder createDan Williams2021-09-211-1/+12
* tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams2021-09-211-15/+21
* cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge portsAlison Schofield2021-09-071-4/+8
* cxl/acpi: Use the ACPI CFMWS to create static decoder objectsAlison Schofield2021-06-171-0/+122
* cxl/acpi: Add the Host Bridge base address to CXL port objectsAlison Schofield2021-06-171-5/+95
* cxl/pmem: Add initial infrastructure for pmem supportDan Williams2021-06-151-2/+35
* cxl/acpi: Introduce cxl_decoder objectsDan Williams2021-06-091-1/+19
* cxl/acpi: Enumerate host bridge root portsDan Williams2021-06-091-1/+92
* cxl/acpi: Add downstream port data to cxl_port instancesDan Williams2021-06-091-1/+42
* cxl/acpi: Introduce the root of a cxl_port topologyDan Williams2021-06-091-0/+39
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 04:10:03 +0000