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path: root/drivers/cxl/core.c
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* cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams2021-06-151-0/+86
* cxl/pmem: Add initial infrastructure for pmem supportDan Williams2021-06-151-0/+121
* cxl/core: Add cxl-bus driver infrastructureDan Williams2021-06-151-0/+73
* cxl/component_regs: Fix offsetBen Widawsky2021-06-121-1/+1
* cxl/hdm: Fix decoder count calculationBen Widawsky2021-06-121-1/+1
* cxl/acpi: Introduce cxl_decoder objectsDan Williams2021-06-091-0/+265
* cxl/acpi: Add downstream port data to cxl_port instancesDan Williams2021-06-091-3/+104
* cxl/acpi: Introduce the root of a cxl_port topologyDan Williams2021-06-091-0/+160
* cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *'Dan Williams2021-06-051-7/+8
* cxl/pci: Add HDM decoder capabilitiesBen Widawsky2021-06-051-0/+92
* cxl/pci: Reserve individual register block regionsIra Weiny2021-06-051-4/+32
* cxl/pci: Map registers based on capabilitiesIra Weiny2021-06-051-12/+62
* cxl/mem: Demarcate vendor specific capability IDsBen Widawsky2021-05-261-1/+4
* cxl/core: Refactor CXL register lookup for bridge reuseDan Williams2021-05-141-0/+57
* cxl/core: Rename bus.c to core.cDan Williams2021-05-141-0/+30