Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Merge branch 'for-6.7/cxl' into for-6.8/cxl | Dan Williams | 2024-01-05 | 1 | -8/+6 |
* | cxl: Fix device reference leak in cxl_port_perf_data_calculate() | Dave Jiang | 2024-01-05 | 1 | -2/+5 |
* | cxl: Convert find_cxl_root() to return a 'struct cxl_root *' | Dave Jiang | 2024-01-05 | 1 | -7/+10 |
* | cxl: Check qos_class validity on memdev probe | Dave Jiang | 2023-12-22 | 1 | -0/+103 |
* | cxl: Store QTG IDs and related info to the CXL memory device context | Dave Jiang | 2023-12-22 | 1 | -0/+69 |
* | cxl: Compute the entire CXL path latency and bandwidth data | Dave Jiang | 2023-12-22 | 1 | -1/+58 |
* | cxl: Add callback to parse the SSLBIS subtable from CDAT | Dave Jiang | 2023-12-22 | 1 | -0/+98 |
* | cxl: Add callback to parse the DSLBIS subtable from CDAT | Dave Jiang | 2023-12-22 | 1 | -2/+100 |
* | cxl: Add callback to parse the DSMAS subtables from CDAT | Dave Jiang | 2023-12-22 | 1 | -0/+92 |