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path: root/drivers/cxl/core/port.c
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* Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams2024-01-051-16/+8
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| * cxl/port: Fix missing target list lockDan Williams2024-01-041-15/+7
| * cxl/port: Fix decoder initialization when nr_targets > interleave_waysHuang Ying2024-01-041-1/+1
* | cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang2024-01-051-2/+2
* | cxl: Introduce put_cxl_root() helperDave Jiang2024-01-051-0/+9
* | cxl: Add helper function that calculate performance data for downstream portsDave Jiang2023-12-221-0/+75
* | cxl: Calculate and store PCI link latency for the downstream portsDave Jiang2023-12-221-0/+6
* | cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang2023-12-221-10/+39
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* cxl/hdm: Fix dpa translation lockingDan Williams2023-12-071-2/+2
* Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams2023-10-311-0/+32
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| * cxl: Add decoders_committed sysfs attribute to cxl_portDave Jiang2023-10-271-0/+25
| * cxl: Add cxl_decoders_committed() helperDave Jiang2023-10-271-0/+7
* | Merge branch 'for-6.7/cxl' into cxl/nextDan Williams2023-10-311-1/+5
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| * | cxl/port: Quiet warning messages from the cxl_test environmentDan Williams2023-09-151-1/+6
* | | Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams2023-10-311-0/+11
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| * | | cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang2023-10-271-0/+11
* | | | Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams2023-10-311-45/+84
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| * | | PCI/AER: Refactor cper_print_aer() for use by CXL driver moduleTerry Bowman2023-10-271-0/+1
| * | | cxl/port: Remove Component Register base address from struct cxl_portRobert Richter2023-10-271-3/+1
| * | | cxl/hdm: Use stored Component Register mappings to map HDM decoder capabilityRobert Richter2023-10-271-7/+22
| * | | cxl/port: Pre-initialize component register mappingsRobert Richter2023-10-271-5/+7
| * | | cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter2023-10-271-3/+3
| * | | cxl/port: Fix @host confusion in cxl_dport_setup_regs()Dan Williams2023-10-271-12/+31
| * | | cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter2023-10-271-2/+2
| * | | cxl/port: Fix delete_endpoint() vs parent unregistration raceDan Williams2023-10-271-15/+19
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* / / cxl/memdev: Fix sanitize vs decoder setup lockingDan Williams2023-10-061-0/+6
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* / cxl/port: Fix cxl_test register enumeration regressionDan Williams2023-09-221-4/+9
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* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-251-45/+105
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| * cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter2023-06-251-0/+11
| * cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter2023-06-251-0/+27
| * cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter2023-06-251-0/+7
| * cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter2023-06-251-1/+0
| * cxl: Rename 'uport' to 'uport_dev'Dan Williams2023-06-251-28/+33
| * cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter2023-06-251-10/+10
| * cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams2023-06-251-2/+2
| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-251-5/+16
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-251-0/+2
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| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-301-0/+2
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* | cxl/memdev: Formalize endpoint port linkageDan Williams2023-06-251-2/+3
* | cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams2023-06-251-3/+3
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* cxl/port: Fix NULL pointer access in devm_cxl_add_port()Robert Richter2023-05-191-4/+3
* Merge tag 'cxl-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds2023-04-301-1/+0
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| * cxl/core: Drop unused io-64-nonatomic-lo-hi.hDan Williams2023-04-181-1/+0
* | Merge tag 'driver-core-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2023-04-271-1/+1
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| * driver core: bus: mark the struct bus_type for sysfs callbacks as constantGreg Kroah-Hartman2023-03-231-1/+1
* | cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams2023-04-041-31/+7
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* Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds2023-02-251-40/+83
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| * Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams2023-02-101-39/+53
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| | * cxl/dax: Create dax devices for CXL RAM regionsDan Williams2023-02-101-1/+3
| | * tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams2023-02-101-0/+2
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