summaryrefslogtreecommitdiffstats
path: root/drivers/cxl/core/port.c
Commit message (Expand)AuthorAgeFilesLines
* cxl/core/port: Fix NULL but dereferenced coccicheck errorWan Jiabing2022-03-221-1/+4
* cxl/port: Hold port reference until decoder releaseDan Williams2022-02-171-0/+4
* cxl/port: Fix endpoint refcount leakDan Williams2022-02-171-1/+2
* cxl/core: Fix cxl_device_lock() class detectionDan Williams2022-02-111-1/+1
* cxl/core/port: Fix unregister_port() lock assertionDan Williams2022-02-111-4/+20
* cxl/core/port: Fix / relax decoder target enumerationDan Williams2022-02-081-1/+4
* cxl/core/port: Add endpoint decodersBen Widawsky2022-02-081-7/+56
* cxl/core: Move target_list out of base decoder attributesDan Williams2022-02-081-1/+2
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-081-4/+101
* cxl/core/port: Add switch port enumerationDan Williams2022-02-081-9/+418
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-081-2/+7
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-081-2/+32
* cxl/core: Emit modalias for CXL devicesDan Williams2022-02-081-9/+17
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-081-12/+45
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-081-39/+52
* cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams2022-02-081-2/+1
* cxl/pmem: Introduce a find_cxl_root() helperDan Williams2022-02-081-0/+49
* cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams2022-02-081-0/+37
* cxl/core/port: Use dedicated lock for decoder target listDan Williams2022-02-081-7/+23
* cxl: Prove CXL lockingDan Williams2022-02-081-11/+36
* cxl/core: Track port depthBen Widawsky2022-02-081-0/+2
* cxl/core/port: Make passthrough decoder init implicitBen Widawsky2022-02-081-1/+8
* cxl/core/port: Clarify decoder creationBen Widawsky2022-02-081-8/+75
* cxl/core: Convert decoder range to resourceBen Widawsky2022-02-081-2/+21
* cxl/decoder: Hide physical address information from non-rootDan Williams2022-02-081-1/+1
* cxl/core/port: Rename bus.c to port.cDan Williams2022-02-081-0/+675
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 06:55:50 +0000