summaryrefslogtreecommitdiffstats
path: root/drivers/cxl/core/regs.c
Commit message (Expand)AuthorAgeFilesLines
* cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter2023-10-271-3/+2
* cxl/core/regs: Rename phys_addr in cxl_map_component_regs()Robert Richter2023-10-271-3/+3
* cxl/pci: Add RCH downstream port AER register discoveryRobert Richter2023-10-271-0/+36
* cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter2023-10-271-14/+14
* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-251-10/+93
|\
| * cxl/regs: Remove early capability checks in Component Register setupRobert Richter2023-06-251-8/+0
| * cxl/pci: Refactor component register discovery for reuseTerry Bowman2023-06-251-0/+77
| * cxl/core/regs: Add @dev to cxl_register_mapRobert Richter2023-06-251-6/+12
| * cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams2023-06-251-2/+3
| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-251-4/+11
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-251-6/+69
|\ \
| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-301-0/+16
| * | cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron2023-05-301-6/+53
| |/
* / cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams2023-06-251-4/+4
|/
* cxl/regs: Fix sparse warningDan Williams2022-12-051-1/+1
* Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams2022-12-051-74/+98
|\
| * cxl/pci: Find and map the RAS Capability StructureDan Williams2022-12-031-0/+7
| * cxl/pci: Prepare for mapping RAS Capability StructureDan Williams2022-12-031-10/+26
| * cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams2022-12-031-17/+23
| * cxl/pci: Cleanup cxl_map_device_regs()Dan Williams2022-12-031-31/+20
| * cxl/pci: Cleanup repeated code in cxl_probe_regs() helpersDan Williams2022-12-031-20/+26
* | cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter2022-12-031-0/+65
* | cxl/core: Check physical address before mapping it in devm_cxl_iomap_block()Robert Richter2022-11-141-0/+3
* | cxl/core: Remove duplicate declaration of devm_cxl_iomap_block()Robert Richter2022-11-141-0/+2
|/
* cxl/regs: Fix size of CXL Capability Header RegisterJonathan Cameron2022-02-081-2/+2
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-081-3/+2
* cxl/pci: Rename pci.h to cxlpci.hDan Williams2022-02-081-1/+1
* cxl/core: Fix cxl_probe_component_regs() error messageDan Williams2022-02-081-1/+1
* cxl/acpi: Map component registers for Root PortsBen Widawsky2022-02-081-0/+56
* cxl/core: Convert to EXPORT_SYMBOL_NS_GPLDan Williams2021-11-151-4/+4
* cxl/registers: Fix Documentation warningDan Williams2021-09-071-1/+14
* cxl/core: Move register mapping infrastructureDan Williams2021-08-061-0/+236
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-29 15:20:38 +0000