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path: root/drivers/cxl/core
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* cxl/core/port: Fix NULL but dereferenced coccicheck errorWan Jiabing2022-03-221-1/+4
* cxl/port: Hold port reference until decoder releaseDan Williams2022-02-171-0/+4
* cxl/port: Fix endpoint refcount leakDan Williams2022-02-171-1/+2
* cxl/core: Fix cxl_device_lock() class detectionDan Williams2022-02-111-1/+1
* cxl/core/port: Fix unregister_port() lock assertionDan Williams2022-02-111-4/+20
* cxl/regs: Fix size of CXL Capability Header RegisterJonathan Cameron2022-02-081-2/+2
* cxl/core/port: Handle invalid decodersDan Williams2022-02-081-6/+30
* cxl/core/port: Fix / relax decoder target enumerationDan Williams2022-02-081-1/+4
* cxl/core/port: Add endpoint decodersBen Widawsky2022-02-082-8/+63
* cxl/core: Move target_list out of base decoder attributesDan Williams2022-02-081-1/+2
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-082-4/+117
* cxl/core/port: Add switch port enumerationDan Williams2022-02-081-9/+418
* cxl/memdev: Add numa_node attributeDan Williams2022-02-081-0/+17
* cxl/pci: Emit device serial numberDan Williams2022-02-081-0/+11
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-083-14/+14
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-082-4/+32
* cxl/core: Emit modalias for CXL devicesDan Williams2022-02-081-9/+17
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-085-15/+298
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-083-39/+154
* cxl/pci: Rename pci.h to cxlpci.hDan Williams2022-02-081-1/+1
* cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams2022-02-081-2/+1
* cxl/pmem: Introduce a find_cxl_root() helperDan Williams2022-02-082-4/+59
* cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams2022-02-081-0/+37
* cxl/core/port: Use dedicated lock for decoder target listDan Williams2022-02-081-7/+23
* cxl: Prove CXL lockingDan Williams2022-02-082-13/+38
* cxl/core: Track port depthBen Widawsky2022-02-081-0/+2
* cxl/core/port: Make passthrough decoder init implicitBen Widawsky2022-02-081-1/+8
* cxl/core: Fix cxl_probe_component_regs() error messageDan Williams2022-02-081-1/+1
* cxl/core/port: Clarify decoder creationBen Widawsky2022-02-081-8/+75
* cxl/core: Convert decoder range to resourceBen Widawsky2022-02-081-2/+21
* cxl/decoder: Hide physical address information from non-rootDan Williams2022-02-081-1/+1
* cxl/core/port: Rename bus.c to port.cDan Williams2022-02-082-1/+1
* cxl/acpi: Map component registers for Root PortsBen Widawsky2022-02-081-0/+56
* cxl/core: Remove cxld_const_init in cxl_decoder_alloc()Nathan Chancellor2022-01-041-4/+2
* cxl/pmem: Fix module reload vs workqueue stateDan Williams2021-11-151-1/+7
* cxl/core: Convert to EXPORT_SYMBOL_NS_GPLDan Williams2021-11-156-29/+29
* cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny2021-11-152-116/+115
* cxl/mbox: Remove bad commentIra Weiny2021-11-151-2/+0
* cxl/core: Split decoder setup into alloc + addDan Williams2021-09-213-93/+48
* tools/testing/cxl: Introduce a mock memory device + driverDan Williams2021-09-211-3/+3
* cxl/mbox: Move command definitions to common locationDan Williams2021-09-211-39/+6
* cxl/bus: Populate the target list at decoder createDan Williams2021-09-211-11/+69
* cxl/pmem: Add support for multiple nvdimm-bridge objectsDan Williams2021-09-211-1/+31
* cxl/mbox: Add exclusive kernel command supportDan Williams2021-09-212-0/+37
* cxl/mbox: Convert 'enabled_cmds' to DECLARE_BITMAPDan Williams2021-09-211-11/+1
* cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the coreDan Williams2021-09-215-9/+910
* cxl/pci: Make 'struct cxl_mem' device type genericDan Williams2021-09-211-4/+3
* Merge tag 'cxl-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds2021-09-091-2/+1
* cxl/registers: Fix Documentation warningDan Williams2021-09-071-1/+14
* cxl/pmem: Fix Documentation warningDan Williams2021-09-071-2/+28
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