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path: root/drivers/cxl/core
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* cxl/core: use sysfs_emit() for attr's _show()Shiyang Ruan2024-01-121-1/+1
* Merge branch 'for-6.8/cxl-cper' into for-6.8/cxlDan Williams2024-01-092-52/+42
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| * cxl/pci: Register for and process CPER eventsIra Weiny2024-01-091-12/+28
| * cxl/events: Create a CXL event unionIra Weiny2024-01-092-23/+17
| * cxl/events: Separate UUID from event structuresIra Weiny2024-01-091-1/+1
| * cxl/events: Remove passing a UUID to known event tracesIra Weiny2024-01-092-15/+19
| * cxl/events: Create common event UUID definesIra Weiny2024-01-091-27/+3
| * cxl/trace: Pass UUID explicitly to event tracesIra Weiny2024-01-032-18/+18
* | Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams2024-01-052-24/+14
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| * | cxl/port: Fix missing target list lockDan Williams2024-01-041-15/+7
| * | cxl/port: Fix decoder initialization when nr_targets > interleave_waysHuang Ying2024-01-041-1/+1
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* | Merge branch 'for-6.8/cxl-misc' into for-6.8/cxlDan Williams2024-01-051-1/+1
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| * | cxl/region: fix x9 interleave typoJim Harris2024-01-031-1/+1
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* | Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlDan Williams2024-01-053-14/+29
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| * | cxl: Refactor to use __free() for cxl_root allocation in cxl_find_nvdimm_brid...Dave Jiang2024-01-051-5/+3
| * | cxl: Fix device reference leak in cxl_port_perf_data_calculate()Dave Jiang2024-01-051-2/+5
| * | cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang2024-01-053-11/+16
| * | cxl: Introduce put_cxl_root() helperDave Jiang2024-01-051-0/+9
* | | Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlDan Williams2024-01-0210-30/+714
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| * | cxl: Check qos_class validity on memdev probeDave Jiang2023-12-221-0/+103
| * | cxl: Store QTG IDs and related info to the CXL memory device contextDave Jiang2023-12-222-0/+71
| * | cxl: Compute the entire CXL path latency and bandwidth dataDave Jiang2023-12-221-1/+58
| * | cxl: Add helper function that calculate performance data for downstream portsDave Jiang2023-12-221-0/+75
| * | cxl: Calculate and store PCI link latency for the downstream portsDave Jiang2023-12-223-0/+44
| * | cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang2023-12-221-10/+39
| * | cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang2023-12-221-0/+98
| * | cxl: Add callback to parse the DSLBIS subtable from CDATDave Jiang2023-12-221-2/+100
| * | cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang2023-12-222-0/+93
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| * cxl/pmu: Ensure put_device on pmu devicesIra Weiny2023-12-141-1/+1
| * cxl/cdat: Free correct buffer on checksum errorIra Weiny2023-12-081-7/+6
| * cxl/hdm: Fix dpa translation lockingDan Williams2023-12-072-4/+3
| * cxl/memdev: Hold region_rwsem during inject and clear poison opsAlison Schofield2023-11-291-2/+16
| * cxl/core: Always hold region_rwsem while reading poison listsAlison Schofield2023-11-292-6/+8
| * cxl/hdm: Fix a benign lockdep splatDave Jiang2023-11-221-0/+2
* | cxl/region: use %pap format to print resource_size_tRandy Dunlap2024-01-021-2/+2
* | cxl/region: Add dev_dbg() detail on failure to allocate HPA spaceAlison Schofield2023-12-241-2/+3
* | cxl: Fix unregister_region() callback parameter assignmentDave Jiang2023-12-181-4/+4
* | cxl: Add Support for Get TimestampDavidlohr Bueso2023-12-071-0/+1
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* cxl/pci: Change CXL AER support check to use native AERTerry Bowman2023-11-021-2/+2
* cxl/hdm: Remove broken error pathDan Williams2023-10-312-17/+10
* cxl/hdm: Fix && vs || bugDan Carpenter2023-10-311-1/+1
* Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams2023-10-314-6/+39
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| * cxl: Add decoders_committed sysfs attribute to cxl_portDave Jiang2023-10-271-0/+25
| * cxl: Add cxl_decoders_committed() helperDave Jiang2023-10-274-6/+14
* | Merge branch 'for-6.7/cxl' into cxl/nextDan Williams2023-10-313-4/+7
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| * | cxl/mbox: Remove useless cast in cxl_mem_create_range_info()Alison Schofield2023-10-241-2/+1
| * | cxl/port: Quiet warning messages from the cxl_test environmentDan Williams2023-09-152-2/+7
* | | Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams2023-10-312-12/+51
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| * | | cxl: Add support for reading CXL switch CDAT tableDave Jiang2023-10-271-5/+17
| * | | cxl: Add checksum verification to CDAT from CXLDave Jiang2023-10-271-7/+23
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