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path: root/drivers/cxl/cxl.h
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* Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams2024-01-051-2/+0
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| * cxl/port: Fix missing target list lockDan Williams2024-01-041-2/+0
* | cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang2024-01-051-7/+7
* | cxl: Introduce put_cxl_root() helperDave Jiang2024-01-051-0/+3
* | cxl: Add helper function that calculate performance data for downstream portsDave Jiang2023-12-221-0/+3
* | cxl: Store the access coordinates for the generic portsDave Jiang2023-12-221-0/+2
* | cxl: Calculate and store PCI link latency for the downstream portsDave Jiang2023-12-221-0/+4
* | cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang2023-12-221-0/+25
* | cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang2023-12-221-0/+4
* | cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang2023-12-221-0/+2
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* Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams2023-10-311-0/+1
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| * cxl: Add cxl_decoders_committed() helperDave Jiang2023-10-271-0/+1
* | Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams2023-10-311-0/+3
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| * | cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang2023-10-271-0/+3
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* | cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter2023-10-271-2/+1
* | cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman2023-10-271-0/+10
* | cxl/pci: Add RCH downstream port AER register discoveryRobert Richter2023-10-271-0/+7
* | cxl/port: Remove Component Register base address from struct cxl_portRobert Richter2023-10-271-2/+0
* | cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter2023-10-271-4/+4
* | cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter2023-10-271-2/+2
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* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-251-25/+32
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| * cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter2023-06-251-0/+2
| * cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter2023-06-251-0/+2
| * cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter2023-06-251-0/+2
| * cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter2023-06-251-2/+0
| * cxl/pci: Refactor component register discovery for reuseTerry Bowman2023-06-251-0/+1
| * cxl/core/regs: Add @dev to cxl_register_mapRobert Richter2023-06-251-4/+6
| * cxl: Rename 'uport' to 'uport_dev'Dan Williams2023-06-251-6/+7
| * cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter2023-06-251-2/+2
| * cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams2023-06-251-2/+7
| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-251-9/+3
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-251-0/+16
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| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-301-0/+13
| * | cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron2023-05-301-0/+3
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* | Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams2023-06-251-7/+9
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| * | cxl/region: Flag partially torn down regions as unusableDan Williams2023-06-251-0/+8
| * | cxl/region: Move cache invalidation before region teardown, and before setupDan Williams2023-06-251-7/+1
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* | Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams2023-06-251-6/+5
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| * | Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams2023-06-251-1/+0
| * | cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams2023-06-251-1/+1
| * | cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams2023-06-251-2/+2
| * | cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams2023-06-251-2/+2
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* / cxl/mbox: Add background cmd handling machineryDavidlohr Bueso2023-05-231-0/+8
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* cxl/port: Enable the HDM decoder capability for switch portsDan Williams2023-05-181-0/+1
* cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams2023-04-041-2/+2
* cxl/hdm: Skip emulation when driver manages mem_enableDan Williams2023-04-041-1/+3
* Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds2023-02-251-2/+94
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| * Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams2023-02-141-2/+18
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| | * cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang2023-02-141-1/+2
| | * cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang2023-02-141-1/+2
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