summaryrefslogtreecommitdiffstats
path: root/drivers/cxl/cxl.h
Commit message (Expand)AuthorAgeFilesLines
* cxl/core: Use is_endpoint_decoderBen Widawsky2022-06-211-0/+1
* cxl: Drop cxl_device_lock()Dan Williams2022-04-281-78/+0
* cxl/core/port: Add endpoint decodersBen Widawsky2022-02-081-0/+1
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-081-0/+6
* cxl/core/port: Add switch port enumerationDan Williams2022-02-081-0/+19
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-081-4/+4
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-081-0/+4
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-081-6/+27
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-081-12/+4
* cxl/pmem: Introduce a find_cxl_root() helperDan Williams2022-02-081-0/+1
* cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams2022-02-081-0/+3
* cxl/core/port: Use dedicated lock for decoder target listDan Williams2022-02-081-0/+2
* cxl: Prove CXL lockingDan Williams2022-02-081-0/+81
* cxl/core: Track port depthBen Widawsky2022-02-081-0/+2
* cxl/core/port: Clarify decoder creationBen Widawsky2022-02-081-1/+15
* cxl/core: Convert decoder range to resourceBen Widawsky2022-02-081-2/+6
* cxl: Introduce module_cxl_driverBen Widawsky2022-02-081-0/+3
* cxl/acpi: Map component registers for Root PortsBen Widawsky2022-02-081-0/+4
* cxl/core: Remove cxld_const_init in cxl_decoder_alloc()Nathan Chancellor2022-01-041-1/+1
* cxl/pmem: Fix module reload vs workqueue stateDan Williams2021-11-151-0/+8
* Merge tag 'cxl-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds2021-11-081-19/+39
|\
| * cxl/pci: Add @base to cxl_register_mapDan Williams2021-10-291-0/+10
| * cxl/core: Split decoder setup into alloc + addDan Williams2021-09-211-9/+6
| * tools/testing/cxl: Introduce a mock memory device + driverDan Williams2021-09-211-1/+1
| * cxl/bus: Populate the target list at decoder createDan Williams2021-09-211-15/+10
| * tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams2021-09-211-0/+16
| * cxl/pmem: Add support for multiple nvdimm-bridge objectsDan Williams2021-09-211-0/+2
* | cxl/core: Replace unions with struct_group()Kees Cook2021-09-251-43/+18
|/
* cxl/pci: Simplify register setupBen Widawsky2021-08-061-1/+0
* cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams2021-06-151-1/+11
* cxl/pmem: Add initial infrastructure for pmem supportDan Williams2021-06-151-0/+24
* cxl/core: Add cxl-bus driver infrastructureDan Williams2021-06-151-0/+22
* cxl/hdm: Fix decoder count calculationBen Widawsky2021-06-121-0/+7
* cxl/acpi: Introduce cxl_decoder objectsDan Williams2021-06-091-0/+63
* cxl/acpi: Add downstream port data to cxl_port instancesDan Williams2021-06-091-0/+21
* cxl/acpi: Introduce the root of a cxl_port topologyDan Williams2021-06-091-0/+31
* cxl/pci: Add HDM decoder capabilitiesBen Widawsky2021-06-051-6/+59
* cxl/pci: Map registers based on capabilitiesIra Weiny2021-06-051-5/+28
* cxl/core: Refactor CXL register lookup for bridge reuseDan Williams2021-05-141-0/+3
* cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams2021-05-141-0/+32
* cxl/mem: Move some definitions to mem.hDan Williams2021-05-141-57/+0
* cxl/mem: Enable commands via CELBen Widawsky2021-02-161-0/+2
* cxl/mem: Register CXL memX devicesDan Williams2021-02-161-0/+3
* cxl/mem: Find device capabilitiesBen Widawsky2021-02-161-0/+90
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-12 04:58:23 +0000