| Commit message (Expand) | Author | Age | Files | Lines |
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| * | cxl: Export sysfs attributes for memory device QoS class | Dave Jiang | 2023-12-22 | 1 | -6/+61 |
| * | cxl/pci: Add RCH downstream port AER register discovery | Robert Richter | 2023-10-27 | 1 | -0/+2 |
| * | cxl/hdm: Use stored Component Register mappings to map HDM decoder capability | Robert Richter | 2023-10-27 | 1 | -3/+2 |
| * | Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl | Dan Williams | 2023-06-25 | 1 | -13/+3 |
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| | * | cxl/pci: Early setup RCH dport component registers from RCRB | Robert Richter | 2023-06-25 | 1 | -9/+0 |
| | * | cxl/mem: Prepare for early RCH dport component register setup | Robert Richter | 2023-06-25 | 1 | -5/+4 |
| | * | cxl: Rename 'uport' to 'uport_dev' | Dan Williams | 2023-06-25 | 1 | -1/+1 |
| | * | cxl/acpi: Probe RCRB later during RCH downstream port creation | Robert Richter | 2023-06-25 | 1 | -2/+2 |
| * | | cxl/mbox: Move mailbox related driver state to its own data structure | Dan Williams | 2023-06-25 | 1 | -3/+7 |
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| * | cxl: Move cxl_await_media_ready() to before capacity info retrieval | Dave Jiang | 2023-05-18 | 1 | -0/+3 |
| * | cxl/mem: Add debugfs attributes for poison inject and clear | Alison Schofield | 2023-04-23 | 1 | -0/+28 |
| * | cxl/memdev: Add trigger_poison_list sysfs attribute | Alison Schofield | 2023-04-23 | 1 | -0/+43 |
| * | cxl/port: Add RCD endpoint port enumeration | Dan Williams | 2022-12-05 | 1 | -8/+25 |
| * | cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem | Dan Williams | 2022-12-05 | 1 | -0/+38 |
| * | cxl/pmem: Refactor nvdimm device registration, delete the workqueue | Dan Williams | 2022-12-02 | 1 | -0/+9 |
| * | cxl/mem: Enumerate port targets before adding endpoints | Dan Williams | 2022-07-21 | 1 | -29/+1 |
| * | cxl/port: Record parent dport when adding ports | Dan Williams | 2022-07-21 | 1 | -4/+6 |
| * | cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem' | Dan Williams | 2022-07-10 | 1 | -0/+23 |
| * | cxl: Fix cleanup of port devices on failure to probe driver. | Jonathan Cameron | 2022-06-21 | 1 | -1/+6 |
| * | cxl/port: Move endpoint HDM Decoder Capability init to port driver | Dan Williams | 2022-05-19 | 1 | -11/+0 |
| * | cxl/pci: Drop @info argument to cxl_hdm_decode_init() | Dan Williams | 2022-05-19 | 1 | -2/+1 |
| * | cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init() | Dan Williams | 2022-05-19 | 1 | -79/+1 |
| * | cxl/mem: Skip range enumeration if mem_enable clear | Dan Williams | 2022-05-19 | 1 | -1/+1 |
| * | cxl/mem: Consolidate CXL DVSEC Range enumeration in the core | Dan Williams | 2022-05-19 | 1 | -6/+8 |
| * | cxl/pci: Move cxl_await_media_ready() to the core | Dan Williams | 2022-05-19 | 1 | -1/+1 |
| * | cxl/mem: Validate port connectivity before dvsec ranges | Dan Williams | 2022-05-19 | 1 | -16/+16 |
| * | cxl/mem: Fix cxl_mem_probe() error exit | Dan Williams | 2022-05-19 | 1 | -2/+4 |
| * | cxl/pci: Consolidate wait_for_media() and wait_for_media_ready() | Dan Williams | 2022-05-19 | 1 | -18/+1 |
| * | cxl/mem: Drop mem_enabled check from wait_for_media() | Dan Williams | 2022-05-19 | 1 | -4/+0 |
| * | cxl: Drop cxl_device_lock() | Dan Williams | 2022-04-28 | 1 | -2/+2 |
| * | PM: CXL: Disable suspend | Dan Williams | 2022-04-22 | 1 | -1/+21 |
| * | cxl/mem: Replace redundant debug message with a comment | Dan Williams | 2022-04-12 | 1 | -4/+10 |
| * | cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init() | Dan Williams | 2022-04-12 | 1 | -6/+6 |
| * | cxl/mem: Make cxl_dvsec_range() init failure fatal | Dan Williams | 2022-04-12 | 1 | -0/+3 |
| * | cxl/mem: Drop DVSEC vs EFI Memory Map sanity check | Dan Williams | 2022-04-12 | 1 | -23/+1 |
| * | cxl/mem: Add the cxl_mem driver | Ben Widawsky | 2022-02-08 | 1 | -0/+228 |
| * | cxl: Rename mem to pci | Ben Widawsky | 2021-05-26 | 1 | -1525/+0 |
| * | cxl/core: Refactor CXL register lookup for bridge reuse | Dan Williams | 2021-05-14 | 1 | -44/+6 |
| * | cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices | Dan Williams | 2021-05-14 | 1 | -20/+24 |
| * | cxl/mem: Move some definitions to mem.h | Dan Williams | 2021-05-14 | 1 | -20/+1 |
| * | cxl/mem: Fix memory device capacity probing | Dan Williams | 2021-04-16 | 1 | -2/+5 |
| * | cxl/mem: Fix register block offset calculation | Ben Widawsky | 2021-04-15 | 1 | -1/+1 |
| * | cxl/mem: Force array size of mem_commands[] to CXL_MEM_COMMAND_ID_MAX | Robert Richter | 2021-04-06 | 1 | -1/+1 |
| * | cxl/mem: Disable cxl device power management | Dan Williams | 2021-04-06 | 1 | -0/+1 |
| * | cxl/mem: Do not rely on device_add() side effects for dev_set_name() failures | Dan Williams | 2021-04-06 | 1 | -10/+29 |
| * | cxl/mem: Fix synchronization mechanism for device removal vs ioctl operations | Dan Williams | 2021-04-06 | 1 | -47/+50 |
| * | cxl/mem: Use sysfs_emit() for attribute show routines | Dan Williams | 2021-04-06 | 1 | -4/+4 |
| * | cxl/mem: Fix potential memory leak | Ben Widawsky | 2021-02-22 | 1 | -1/+3 |
| * | cxl/mem: Return -EFAULT if copy_to_user() fails | Dan Carpenter | 2021-02-19 | 1 | -1/+4 |
| * | cxl/mem: Add set of informational commands | Ben Widawsky | 2021-02-16 | 1 | -0/+9 |
