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path: root/drivers/cxl/pci.c
Commit message (Expand)AuthorAgeFilesLines
* cxl: Move cxl_await_media_ready() to before capacity info retrievalDave Jiang2023-05-181-0/+6
* Merge branch 'for-6.4/cxl-poison' into for-6.4/cxlDan Williams2023-04-231-0/+4
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| * cxl/mbox: Initialize the poison stateAlison Schofield2023-04-231-0/+4
* | cxl/pci: Use CDAT DOE mailbox created by PCI coreLukas Wunner2023-04-181-49/+0
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* Merge branch 'for-6.3/cxl' into cxl/nextDan Williams2023-02-141-8/+62
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| * cxl: add RAS status unmasking for CXLDave Jiang2023-02-141-0/+65
| * cxl: remove unnecessary calling of pci_enable_pcie_error_reporting()Dave Jiang2023-02-141-11/+0
* | cxl/pci: Fix irq oneshot expectationsDan Williams2023-01-301-1/+2
* | cxl/pci: Set the device timestampJonathan Cameron2023-01-301-0/+4
* | cxl/mem: Wire up event interruptsDavidlohr Bueso2023-01-261-10/+211
* | cxl/mem: Read, trace, and clear events on driver loadIra Weiny2023-01-261-0/+33
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* cxl/pci: Show opcode in debug messages when sending a commandRobert Richter2023-01-241-1/+1
* cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams2023-01-041-111/+0
* cxl/pci: Remove endian confusionDan Williams2022-12-061-4/+3
* cxl/pci: Add some type-safety to the AER trace pointsDan Williams2022-12-061-2/+2
* Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams2022-12-051-40/+173
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| * cxl/pci: Add callback to log AER correctable errorDave Jiang2022-12-031-0/+20
| * cxl/pci: Add (hopeful) error handling supportDan Williams2022-12-031-0/+137
| * cxl/pci: add tracepoint events for CXL RASDave Jiang2022-12-031-0/+2
| * cxl/pci: Find and map the RAS Capability StructureDan Williams2022-12-031-0/+8
| * cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams2022-12-031-19/+6
| * cxl/pci: Kill cxl_map_regs()Dan Williams2022-12-031-22/+1
* | cxl/port: Add RCD endpoint port enumerationDan Williams2022-12-051-0/+10
* | cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams2022-12-021-3/+0
* | cxl/doe: Request exclusive DOE accessIra Weiny2022-11-141-0/+5
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* cxl/pci: Create PCI DOE mailbox's for memory devicesIra Weiny2022-07-191-0/+44
* cxl/mem: Convert partition-info to resourcesDan Williams2022-07-091-1/+1
* cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams2022-05-191-135/+0
* cxl/pci: Move cxl_await_media_ready() to the coreDan Williams2022-05-191-44/+1
* cxl/pci: Drop wait_for_valid() from cxl_await_media_ready()Dan Williams2022-05-191-4/+0
* cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()Dan Williams2022-05-191-2/+2
* cxl/pci: Make cxl_dvsec_ranges() failure not fatal to cxl_pciDan Williams2022-04-121-9/+18
* cxl/pci: Add debug for DVSEC range init failuresDan Williams2022-04-121-3/+10
* cxl/mbox: Use new return_code handlingDavidlohr Bueso2022-04-121-1/+2
* cxl/mbox: Improve handling of mbox_cmd hw return codesDavidlohr Bueso2022-04-121-1/+1
* cxl/pci: Use CXL_MBOX_SUCCESS to check against mbox_cmd return codeDavidlohr Bueso2022-04-121-2/+2
* cxl/pci: Drop shadowed variableDan Williams2022-04-081-1/+0
* cxl/pci: Emit device serial numberDan Williams2022-02-081-0/+1
* cxl/pci: Implement wait for media activeBen Widawsky2022-02-081-1/+48
* cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky2022-02-081-0/+119
* cxl/pci: Cache device DVSEC offsetBen Widawsky2022-02-081-0/+6
* cxl/pci: Store component register base in cxldsBen Widawsky2022-02-081-0/+11
* cxl/pci: Rename pci.h to cxlpci.hDan Williams2022-02-081-1/+1
* cxl/acpi: Map component registers for Root PortsBen Widawsky2022-02-081-52/+0
* cxl: Flesh out register namesBen Widawsky2022-02-081-7/+7
* cxl/pci: Defer mailbox status checks to command timeoutsDan Williams2022-02-081-101/+33
* cxl/pci: Implement Interface Ready TimeoutBen Widawsky2022-02-081-0/+35
* cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny2021-11-151-60/+60
* cxl/pci: Use pci core's DVSEC functionalityBen Widawsky2021-10-291-24/+2
* cxl/pci: Split cxl_pci_setup_regs()Ben Widawsky2021-10-291-36/+37
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