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path: root/drivers/cxl
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* cxl/pci: Rename CXL REGLOC IDBen Widawsky2021-06-172-2/+2
* cxl/acpi: Use the ACPI CFMWS to create static decoder objectsAlison Schofield2021-06-171-0/+122
* cxl/acpi: Add the Host Bridge base address to CXL port objectsAlison Schofield2021-06-171-5/+95
* cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams2021-06-155-16/+215
* cxl/pmem: Add initial infrastructure for pmem supportDan Williams2021-06-156-2/+335
* cxl/core: Add cxl-bus driver infrastructureDan Williams2021-06-152-0/+95
* cxl/pci: Add media provisioning required commandsBen Widawsky2021-06-141-0/+19
* cxl/component_regs: Fix offsetBen Widawsky2021-06-121-1/+1
* cxl/hdm: Fix decoder count calculationBen Widawsky2021-06-122-1/+8
* cxl/acpi: Introduce cxl_decoder objectsDan Williams2021-06-093-1/+347
* cxl/acpi: Enumerate host bridge root portsDan Williams2021-06-091-1/+92
* cxl/acpi: Add downstream port data to cxl_port instancesDan Williams2021-06-093-4/+167
* cxl/Kconfig: Default drivers to CONFIG_CXL_BUSDan Williams2021-06-091-0/+2
* cxl/acpi: Introduce the root of a cxl_port topologyDan Williams2021-06-095-0/+247
* cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *'Dan Williams2021-06-051-7/+8
* cxl/pci: Add HDM decoder capabilitiesBen Widawsky2021-06-053-6/+166
* cxl/pci: Reserve individual register block regionsIra Weiny2021-06-052-4/+34
* cxl/pci: Map registers based on capabilitiesIra Weiny2021-06-053-38/+180
* cxl/pci: Reserve all device regions at onceIra Weiny2021-06-051-7/+11
* cxl/pci: Introduce cxl_decode_register_block()Ira Weiny2021-06-051-8/+18
* cxl/mem: Get rid of @cxlm.baseBen Widawsky2021-05-262-15/+11
* cxl/mem: Move register locator logic into reg setupBen Widawsky2021-05-261-67/+68
* cxl/mem: Split creation from mapping in probeBen Widawsky2021-05-261-24/+40
* cxl/mem: Use dev instead of pdev->devBen Widawsky2021-05-261-1/+1
* cxl/mem: Demarcate vendor specific capability IDsBen Widawsky2021-05-261-1/+4
* cxl/pci.c: Add a 'label_storage_size' attribute to the memdevVishal Verma2021-05-262-0/+15
* cxl: Rename mem to pciBen Widawsky2021-05-263-16/+10
* cxl/core: Refactor CXL register lookup for bridge reuseDan Williams2021-05-143-44/+66
* cxl/core: Rename bus.c to core.cDan Williams2021-05-142-9/+10
* cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams2021-05-143-28/+61
* cxl/mem: Move some definitions to mem.hDan Williams2021-05-143-77/+82
* cxl/mem: Fix memory device capacity probingDan Williams2021-04-161-2/+5
* cxl/mem: Fix register block offset calculationBen Widawsky2021-04-151-1/+1
* cxl/mem: Force array size of mem_commands[] to CXL_MEM_COMMAND_ID_MAXRobert Richter2021-04-061-1/+1
* cxl/mem: Disable cxl device power managementDan Williams2021-04-061-0/+1
* cxl/mem: Do not rely on device_add() side effects for dev_set_name() failuresDan Williams2021-04-061-10/+29
* cxl/mem: Fix synchronization mechanism for device removal vs ioctl operationsDan Williams2021-04-061-47/+50
* cxl/mem: Use sysfs_emit() for attribute show routinesDan Williams2021-04-061-4/+4
* cxl/mem: Fix potential memory leakBen Widawsky2021-02-221-1/+3
* cxl/mem: Return -EFAULT if copy_to_user() failsDan Carpenter2021-02-191-1/+4
* cxl/mem: Add set of informational commandsBen Widawsky2021-02-161-0/+9
* cxl/mem: Enable commands via CELBen Widawsky2021-02-162-7/+218
* cxl/mem: Add a "RAW" send commandBen Widawsky2021-02-162-0/+150
* cxl/mem: Add basic IOCTL interfaceBen Widawsky2021-02-161-1/+282
* cxl/mem: Register CXL memX devicesDan Williams2021-02-164-2/+318
* cxl/mem: Find device capabilitiesBen Widawsky2021-02-163-2/+679
* cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpointsDan Williams2021-02-164-0/+118
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 07:09:58 +0000