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path: root/drivers/edac/i10nm_base.c
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* EDAC/i10nm: Add Intel Sierra Forest server supportQiuxu Zhuo2023-04-101-0/+1
* EDAC/i10nm: Add driver decoder for Sapphire Rapids serverYouquan Song2023-02-081-33/+69
* EDAC/i10nm: Add Intel Granite Rapids server supportQiuxu Zhuo2023-01-251-23/+214
* EDAC/i10nm: Make more configurations CPU model specificQiuxu Zhuo2023-01-251-40/+91
* EDAC/i10nm: Add Intel Emerald Rapids server supportQiuxu Zhuo2023-01-251-0/+1
* Merge branches 'edac-ghes' and 'edac-misc' into edac-updates-for-v6.2Borislav Petkov (AMD)2022-12-121-2/+1
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| * EDAC/i10nm: fix refcount leak in pci_get_dev_wrapper()Yang Yingliang2022-11-281-2/+1
* | EDAC: Check for GHES preference in the chipset-specific EDAC driversJia He2022-10-211-0/+3
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* EDAC/i10nm: Print an extra register set of retry_rd_err_logQiuxu Zhuo2022-09-231-11/+70
* EDAC/i10nm: Retrieve and print retry_rd_err_log registers for HBMQiuxu Zhuo2022-09-231-17/+67
* EDAC/i10nm: Add driver decoder for Ice Lake and Tremont CPUsYouquan Song2022-09-081-2/+132
* EDAC/i10nm: Release mdev/mbase when failing to detect HBMQiuxu Zhuo2022-01-041-0/+9
* EDAC/i10nm: Retrieve and print retry_rd_err_log registersYouquan Song2021-08-231-0/+146
* EDAC/i10nm: Fix NVDIMM detectionQiuxu Zhuo2021-08-231-3/+3
* EDAC/Intel: Do not load EDAC driver when running as a guestLuck, Tony2021-06-171-0/+3
* EDAC/i10nm: Add support for high bandwidth memoryQiuxu Zhuo2021-06-171-12/+120
* EDAC/i10nm: Add detection of memory levels for ICX/SPR serversQiuxu Zhuo2021-06-171-0/+39
* EDAC/i10nm: Add Intel Sapphire Rapids server supportQiuxu Zhuo2020-11-191-9/+25
* EDAC/i10nm: Use readl() to access MMIO registersQiuxu Zhuo2020-11-191-4/+7
* EDAC, {skx,i10nm}: Use CPU stepping macro to pass configurationsQiuxu Zhuo2020-06-151-7/+5
*-. Merge branches 'edac-i10nm' and 'edac-misc' into edac-updates-for-5.8Borislav Petkov2020-06-011-5/+24
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| | * EDAC/skx: Use the mcmtr register to retrieve close_pg/bank_xor_enableQiuxu Zhuo2020-05-191-1/+1
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| * EDAC/i10nm: Update driver to support different bus number config register off...Qiuxu Zhuo2020-04-271-4/+14
| * EDAC, {skx,i10nm}: Make some configurations CPU model specificQiuxu Zhuo2020-04-271-4/+13
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* EDAC: Convert to new X86 CPU match macrosThomas Gleixner2020-03-241-4/+4
* EDAC: Replace EDAC_DIMM_PTR() macro with edac_get_dimm() functionRobert Richter2019-11-091-2/+1
* x86/intel: Aggregate microserver namingPeter Zijlstra2019-08-281-2/+2
* EDAC, skx, i10nm: Fix source ID register offsetQiuxu Zhuo2019-06-261-1/+1
* EDAC, i10nm: Check ECC enabling status per channelQiuxu Zhuo2019-06-261-3/+3
* EDAC, i10nm: Add Intel additional Ice-Lake supportQiuxu Zhuo2019-06-201-0/+2
* EDAC, skx, i10nm: Make skx_common.c a pure libraryQiuxu Zhuo2019-03-231-2/+50
* EDAC, i10nm: Add a driver for Intel 10nm server processorsQiuxu Zhuo2019-02-021-0/+275