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path: root/drivers/gpu/drm/amd/display/dc/dc.h
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* drm/amd/display: Promote DAL to 3.2.262Aric Cyr2023-11-291-1/+1
| | | | | | | | | | | | | | | | This version brings along following fixes: - Add DSC granular throughput adjustment - Allow DTBCLK disable for DCN35 - Update Fixed VS/PE Retimer Sequence - Block dcn315 dynamic crb allocation when unintended - Update dcn315 lpddr pstate latency - Fix some HostVM parameters in DML Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.261Aric Cyr2023-11-291-1/+1
| | | | | | | | | | | | | | | | | This version brings along the following: - DCN314 fixes - DCN32 fixes - DCN35 fixes - DML2 fixes - eDP fixes - HDR fixes - MST fixes - Replay fixes - SubVP support for more configs Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: adjust flow for deallocation mst payloadWayne Lin2023-11-291-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] MST relevant variables are maintained at drm side. As the result, we still have to call drm_dp_remove_payload_part2() to update the relevant values regardless the link is under mst mode or not. We used to have a workaround patch to tackle this: commit 3d8fcc6740c9 ("drm/amd/display: Extract temp drm mst deallocation wa into its own function") Now it's time to remove the workaround and adjust the flow. [How] During deallocate_mst_payload(), source actually doesn't send out ALLOCATE_PAYLOAD at the end as like the flow in allocate_mst_payload(). Call function dm_helpers_dp_mst_send_payload_allocation() at the end of deallocate_mst_payload() is a bit confusing. Separate dm_helpers_dp_mst_send_payload_allocation() into 2 functions. Have a new function dm_helpers_dp_mst_update_mst_mgr_for_deallocation() to replace dm_helpers_dp_mst_send_payload_allocation() for payload deallocation. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Simplify brightness initializationCamille Cho2023-11-291-1/+0
| | | | | | | | | | | | | | | | | | | [Why] Remove the brightness cache in DC. It uses a single value to represent the brightness for both SDR and HDR mode. This leads to flash in HDR on/off. It also unconditionally programs brightness as in HDR mode. This may introduce garbage on SDR mode in miniLED panel. [How] Simplify the initialization flow by removing the DC cache and taking what panel has as default. Expand the mechanism for PWM to DPCD Aux to restore cached brightness value generally. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Camille Cho <camille.cho@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add z-state support policy for dcn35Nicholas Kazlauskas2023-11-291-0/+1
| | | | | | | | | | | | | | | | | | | [Why] DML2 means that the dcn3x policy for calculating z-state support no longer runs from validate_bandwidth. This means we are unconditionally allowing Z8, the hardware default. [How] Port the policy over to DCN35, but with a few modifications: - Don't use min_dst_y_next_start as a check for Z8/Z10 allow - Add support for overriding the Z10 stutter period per ASIC - Cleanup the code to make the policy assignment more clear Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Promote DC to 3.2.260Aric Cyr2023-11-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | - Add missing chips for HDCP - Add new command to disable replay timing resync - Fix encoder disable logic - Enable DSC Flag in MST Mode Validation - Change the DMCUB mailbox memory location from FB to inbox - Add disable timeout option - Negate IPS allow and commit bits - Enable DCN clock gating for DCN35 - Prefer currently used OTG master when acquiring free pipe - Try to acquire a free OTG master not used in cur ctx first - Clear dpcd_sink_ext_caps if not set - Enable fast plane updates on DCN3.2 and above - Add null checks for 8K60 lightup - Refactor resource into component directory - Fix DSC not Enabled on Direct MST Sink - Guard against invalid RPTR/WPTR being set - Enable CM low mem power optimization - Fix a debugfs null pointer error Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add disable timeout optionDuncan Ma2023-11-171-0/+1
| | | | | | | | | | | | | | | | | | | [WHY] Driver continues running whenever there is is timeout from smu or dmcub. It is difficult to track failure state when dcn, dc or dmcub changes on root failure. [HOW] Add disable_timeout option to halt driver whenever there is a failure in response. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Promote DAL to 3.2.259Aric Cyr2023-11-071-1/+1
| | | | | | | | | | | | | | | | | | | Summary: - Enable DCN35 physymclk root clock gating - Fix DP automation test pattern bug - Disable OTG for mode timing switch on DCN35 - Refactor DML2 - Revert Fix handling duplicate planes on one stream - Revert Enable DCN clock gating - Implement cursor P-State allow for SubVP - Optimize pipe otg allocation - Save and restore mall state while switching from ODM to Subvp Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.258Aric Cyr2023-11-071-1/+1
| | | | | | | | | | | | | | | | | | | | | This version brings along following fixes: Update test link rate DPCD bit field to match spec Enable RCO options for dcn35 Add missing dml2 init value for dcn35 Enable DCN clock gating DCN35 Disable cm power optimization Allow 16 max_slices for DP2 DSC Fix OTG disable workaround logic Enable more IPS options Fix FRL assertion on boot Fix missing blendTF programming Update DP HPO MSA with colorimetry from test request Fix handling duplicate planes on one stream Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.257Aric Cyr2023-11-071-1/+1
| | | | | | | | | | | | | | | | This version brings along following fixes: On boot disable domain22 force power on decouple dmcub execution to reduce lock granularity Enable fast update on blendTF change Fix blend LUT programming Program plane color setting correctly amend HPD handler for Replay Avoid NULL dereference of timing generator Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.256Aric Cyr2023-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | DC v3.2.256 Summary: * Fixes null-deref regression after "drm/amd/display: Update OPP counter from new interface" * Fixes display flashing when VSR and HDR enabled on dcn32 * Fixes dcn3x intermittent hangs due to FPO * Fixes MST Multi-Stream light up on dcn35 * Fixes green screen on DCN31x when DVI and HDMI monitors attached * Adds DML2 improvements * Adds idle power optimization improvements * Accommodates panels with lower nit backlight * Updates SDP VSC colorimetry from DP test automation request * Reverts "drm/amd/display: allow edp updates for virtual signal" Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add interface to query SubVP statusAurabindo Pillai2023-10-261-0/+1
| | | | | | | | | | | | [Why&How] To enable automated testing through IGT, expose an API that is accessible through debugfs to query current status of SubVP feature. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix IPS handshake for idle optimizationsNicholas Kazlauskas2023-10-261-0/+2
| | | | | | | | | | | | | | | | | | | | [Why] Intermittent reboot hangs are observed introduced by "Improve x86 and dmub ips handshake". [How] Bring back the commit but fix the polling. Avoid hanging in place forever by bounding the delay and ensure that we still message DMCUB on IPS2 exit to notify driver idle has been cleared. Reviewed-by: Duncan Ma <duncan.ma@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add a check for idle power optimizationSung Joon Kim2023-10-261-0/+1
| | | | | | | | | | | | | | | | | | | | | [why] Need a helper function to check idle power is allowed so that dc doesn't access any registers that are power-gated. [how] Implement helper function to check idle power optimization. Enable a hook to check if detection is allowed. V2: Add function hooks for set and get idle states. Check if function hook was properly initialized. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Nicholas Choi <nicholas.choi@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Revert "Improve x86 and dmub ips handshake"Nicholas Kazlauskas2023-10-261-2/+0
| | | | | | | | | | | | This reverts commit 1288d702080949f87688d49dfeeacc99f40adc9b. Causes intermittent hangs during reboot stress testing. Reviewed-by: Duncan Ma <duncan.ma@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: make dc_set_power_state() return type `void` againMario Limonciello2023-10-131-1/+1
| | | | | | | | | | | As dc_set_power_state() no longer allocates memory, it's not necessary to have return types and check return code as it can't fail anymore. Change it back to `void`. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.255Aric Cyr2023-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | This version brings along following fixes: - Refactor DPG test pattern logic for ODM cases - Refactor HWSS into component folder - Revert "drm/amd/display: Add a check for idle power optimization" - Revert "drm/amd/display: remove duplicated edp relink to fastboot - Update cursor limits based on SW cursor fallback limits - Update stream mask - Update pmfw_driver_if new structure - Modify SMU message logs - Don't set dpms_off for seamless boot Known issue: DWB (Writeback functionality) is broken. Fix will be available in DC 3.2.256 Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Refactor HWSS into component folderMounika Adhuri2023-10-091-1/+1
| | | | | | | | | | | | | | | | | | | [why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Mounika Adhuri <moadhuri@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Revert "drm/amd/display: Add a check for idle power ↵Sung Joon Kim2023-10-091-1/+0
| | | | | | | | | | | | | optimization" Revert commit 434cf7af492f ("drm/amd/display: Add a check for idle power optimization") Because it cause Freesync and S4 regression Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Modify SMU message logsSung Joon Kim2023-10-091-0/+1
| | | | | | | | | | | | | | | | | [why] It's important to make sure SMU messages are logged by default to improve debugging for power optimization use cases. [how] Change logs to warnings when SMU message returns non-success id. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Introduce DML2Qingqing Zhuo2023-10-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Co-developed-by: Roman Li <roman.li@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.254Aric Cyr2023-10-041-1/+1
| | | | | | | | | | | | | | | | | | DC v3.2.254 * Stability fixes through null pointer checks, blackscreen fixes on certain configurations * Improvements for various functionality like Idle optimization, ILR, DSC, IPS * Fixes for ILR functionality * Trivial code cleanups =================================================================== Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add a check for idle power optimizationSung Joon Kim2023-10-041-0/+1
| | | | | | | | | | | | | | | | [why] Need a helper function to check idle power is allowed so that dc doesn't access any registers that are power-gated. [how] Implement helper function to check idle power optimization. Enable a hook to check if detection is allowed. Signed-off-by: Sung Joon Kim <Sungjoon.Kim@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: use full update for clip size increase of large plane sourceWenjing Liu2023-10-041-0/+5
| | | | | | | | | | | | | | | | | [why] Clip size increase will increase viewport, which could cause us to switch to MPC combine. If we skip full update, we are not able to change to MPC combine in fast update. This will cause corruption showing on the video plane. [how] treat clip size increase of a surface larger than 5k as a full update. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Make driver backwards-compatible with non-IPS PMFWOvidiu Bunea2023-10-041-1/+1
| | | | | | | | | | | | | | [why] Driver needs to be compatible with PM FW that doesn't support IPS [how] Toggle internal control flag Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Change dc_set_power_state() to bool instead of intMario Limonciello2023-09-261-1/+1
| | | | | | | | | | | | DC code is reused by other OSes and so Linux return codes don't make sense. Change dc_set_power_state() to boolean and add a wrapper dm_set_power_state() to return a Linux error code for the memory allocation failure. Suggested-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd: Propagate failures in dc_set_power_state()Mario Limonciello2023-09-261-1/+1
| | | | | | | | | | | | During the suspend process dc_set_power_state() will use kzalloc to allocate memory, but this potentially fails with memory pressure. If it fails, the suspend should be aborted. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: Harry.Wentland@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: augment display clock in dc_cap structureMax Tseng2023-09-261-0/+1
| | | | | | | | | | | [Why] Allow dc report maximum display clock possible at vmin Reviewed-by: Wayne Lin <wayne.lin@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Max Tseng <max.tseng@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.253Aric Cyr2023-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This version brings along the following: - Fix incorrect odm change detection logic - Add primary pipe check when building slice table for dcn3x - Add get primary dpp pipe resource interface - Add missing function pointer for DCN321 resource - Rename DisableMinDispClkODM in dc_config - Break after finding supported vlevel for repopulate - Update OPP counter from new interface - Augment display clock in dc_cap structure - Improve code style on bios_parser2 - Skip audio config for virtual signal - Block MPO if it prevents pstate support - Fix DP2.0 timing sync - Improve x86 and dmub ips handshake - Remove guaranteed viewports limitation for odm - Add new windowed mpo odm minimal transition sequence - Reset stream slice count for new ODM policy - Determine fast update only before commit minimal transition state - Remove unused mmhub_reg_offsets Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Rename DisableMinDispClkODM in dc_configGabe Teeger2023-09-261-1/+1
| | | | | | | | | | | | [what and why] The logic for DisableMinDispClkODM is reversed now that odm is disabled by default. Renaming to EnableMinDispClkODM. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: block MPO if it prevents pstate supportDmytro Laktyushkin2023-09-261-0/+6
| | | | | | | | | | | | | This change adds a method to block mpo when it would cause us to exit pstate support. We should block mpo by default where MPO causes issues by preventing pstate change. Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Improve x86 and dmub ips handshakeDuncan Ma2023-09-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | [Why] There is a race condition between x86 and dmcub fw when attempting to exit IPS2. Scenarios including exiting IPS2 before IPS2 has been entered. This can cause unexpected hang when DMCUB attempt to exit while PMFW still tries to enter IPS2. [How] A new design has been introduced to remove race conditions and improve the handshake between x86 and DMCUB. An AON scratch register is borrowed from PMFW to determine whether DMCUB has committed to IPS entry or not. In the case when dmcub has committed IPS entry, x86 must poll until an exit event occurred either from DMCUB(IPS1) or PMFW(IPS2). x86 will wait upperbound of evaluation and IPS entry time to ensure IPS2 exit event has been sent to PMFW. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.252Aric Cyr2023-09-261-1/+1
| | | | | | | | | | | | | | | | | | This version brings along the following: - Use optc32 instead of optc30 in DC - Optimize OLED T7 delay - Multiple fixes for MST, register mas, and others - Update driver and IPS interop - Improve z8 watermark mask - DCN35 updates - Enable replay for DCN35 - Temporarily disable clock gating Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.251Aric Cyr2023-09-201-1/+1
| | | | | | Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add option to flip ODM optimizationGabe Teeger2023-09-201-0/+1
| | | | | | | | | | | Add a config option to disable odm dispclk optimization for debug purpose. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.250Aric Cyr2023-09-111-1/+1
| | | | | | | Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add new logs for AutoDPMTestEthan Bitnun2023-09-111-0/+1
| | | | | | | | | | | | | [Description] - Add new logs to be used by the AutoDPMTest - Enclose AutoDPMTest logs in settings - Add logging definition Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Ethan Bitnun <etbitnun@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DCN35 CLK_MGRQingqing Zhuo2023-08-301-0/+2
| | | | | | | | | | | [Why & How] Add CLK_MGR handling for DCN35. v2: Drop stale SMU interfaces (Alex) Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Update dc.h for DCN35 supportQingqing Zhuo2023-08-301-0/+56
| | | | | | | | | [Why & How] Update dc.h for DCN35 usage. Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.249Martin Leung2023-08-301-1/+1
| | | | | | | | | | | | | | | | | This version brings along the following: - DCN315 fixes - DCN31 fixes - DPIA fixes - Dump the pipe topology when it updates - Misc code cleanups - New debugfs interface to query the current ODM combine configuration - ODM fixes - Potential deadlock while waiting for MPC idle fix - Support for windowed MPO ODM Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DPIA Link Encoder Assignment FixMustapha Ghaddar2023-08-301-0/+1
| | | | | | | | | | For DPIA we should have preferred DIG assignment based on DPIA selected as per the ASIC design. Reviewed-by: George Shen <george.shen@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.248Aric Cyr2023-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | This version brings along following fixes: - Ensure FS is enabled before sending request to DMUB for FS changes - Add check for PMFW hard min request complete - Save addr update in scratch before flip - Fix static screen detection setting - Write flip addr to scratch reg for subvp - set minimum of VBlank_nom - Correct unit conversion for vstartup - Roll back unit correction - Enable runtime register offset init for DCN32 DMUB - Refactor edp power control - PQ regamma end point - PQ tail accuracy - Expose mall capability Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Refactor edp power controlIan Chen2023-08-301-0/+4
| | | | | | | | | | | | | | | [Why & How] To organize the edp power control a bit: 1. add flag in dc_link to indicate dc to skip all implicit eDP power control. 2. add edp_set_panel_power link service for DM to call. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Promote DAL to 3.2.247Aric Cyr2023-08-151-1/+1
| | | | | | | | | | | | | | | | | This version brings along following fixes: - Improve power saving feature - Clean up for code clarity - Fix crashing bug - Fix pipe allocation for older ASIC - Fix for gamut remap - Fix 8K 60Hz display in test cases - Fix bug in clock gating - Improve DP2 compliance Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Support Compliance Test Pattern Generation with DP2 RetimerMichael Strauss2023-08-151-0/+1
| | | | | | | | | | | | | | | | | [WHY] Certain retimer requires workarounds in order to correctly output test patterns. [HOW] Add vendor-specific aux sequences to program retimer's TX and pattern generator when specific compliance test patterns are requested by sink. Note: SQ128 w/a in DPMF mode only works in one flip orientation currently Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Promote DAL to 3.2.246Martin Leung2023-08-071-1/+1
| | | | | | | | | | | | | | | | | | This version brings along following fixes: - Fix a regression in blank pixel data caused by coding mistake - Fix a bug when searching for insert_above_mpcc - Update add plane to context logic with a new algorithm - Adjust visual confirm dpp height offset to be 1/240 of v addressable - Add interface to enable DPIA trace - Support plane clip with zero recout size - Blocking invalid 420 modes on HDMI TMDS for DCN31 and DCN314 - Make mpc32 functions available to future DCNs - Change HDCP update sequence for DM Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Martin Leung <martin.leung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add Freesync Panel DM codeBhawanpreet Lakha2023-08-071-0/+2
| | | | | | | | | We need certain conditions for replay to be enabled, so create an interface in DM to enable/disable replay. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Promote DC to 2.3.245Aric Cyr2023-08-071-1/+1
| | | | | | | Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Implement interface for notify cursor support changeAlvin Lee2023-08-071-0/+10
| | | | | | | | | | | [Description] Add new interface for notifying OS of cursor support changes Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add structs for Freesync Panel ReplayBhawanpreet Lakha2023-08-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | In some instances, the GPU is transmitting repeated frame to the sink without any updates or changes in the content. These repeat transmission are wasteful, resulting in power draw in different aspects of the system 1. DCN is fetching the frame of data from DF/UMC/DRAM. This memory traffic prevents power down of parts of this HW path. 2. GPU is transmitting pixel data to the display through the main link of the DisplayPort interface. This prevents power down of both the Source transmitter (TX) and the Sink receiver (RX)  The concepts of utilizing replay is similar to PSR, but there is a benefit of: Source and Sink remaining synchronized which allows for - lower latency when switching from replay to live frames - enable the possibility of more use cases - easy control of the sink's refresh rate during replay Due to Source and Sink remaining timing synchronized, Replay can be activated in more UI scenarios. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-31 20:41:21 +0000