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path: root/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
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* drm/amd/display: Adjust code style for hw_sequencer.hAurabindo Pillai2023-10-041-7/+0
| | | | | | | | | | | [Why&How] * Rearrange some definitions for consistency * Drop legacy code Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Rename DCN config to FPHarry Wentland2023-03-071-1/+1
| | | | | | | | | | | | | | [Why & How] The only reason we have the DCN config is for floating point support. Rename it to make that clear and (hopefully) avoid misuse of the config in the future. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: merge dc_link.h into dc.h and dc_types.hWenjing Liu2023-02-281-0/+14
| | | | | | | | | | | | | | | | [why] Remove the need to include dc_link.h separately. dc.h should contain everything needed on DM side. [How] Merge dc_link.h into dc.h and dc_types.h so DM only needs to include dc.h to use all link public functions. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add rc_params_override option in dc_dsc_configWenjing Liu2023-01-311-0/+24
| | | | | | | | | | | | | | | [why] Current RC params are based on VESA recommended configurations. Some DSC sink may prefer non standard rc params values due to hardware limitations. To support those DSC sink we will allow DM to optionally pass rc_params_ovrd in dc_dsc_config so DC will override the default VESA recommended configurations. Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Expand documentation for timingRodrigo Siqueira2022-08-161-0/+86
| | | | | | | | | | | | | | The timing programming inside DCN is far from trivial, it has multiple parameters associated with that, and the lack of documentation does not help comprehend this already complicated topic. This commit tries to improve this situation by expanding the documentation of dc_crtc_timing and the VTG program function. Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add documentation to some of the cursor structRodrigo Siqueira2022-08-161-7/+55
| | | | | | | | Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: OVT Update on InfoFrame and Mode ManagementChris Park2022-07-051-0/+2
| | | | | | | | | | | | | | | | [Why] Integrate OVT timing from DM to DC logic to update info frame and mode management to report the resolution to the OS. [How] Reflect RID and Frame Rate to AVI InfoFrame Version 5. Define new Timing Standard for OVT timing. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Chris Park <Chris.Park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add dependant changes for DCN32/321Aurabindo Pillai2022-06-031-0/+1
| | | | | | | | | | | | [Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: move definition of dc_flip_addrs structJosip Pavic2022-05-101-0/+16
| | | | | | | | | | | | [Why & How] Move definition of dc_flip_addrs struct from dc.h to dc_hw_types.h to prevent build errors Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Clean up pixel format typesAric Cyr2022-05-041-1/+2
| | | | | | | | | | | | [Why & How] Equate the first non-subsampled video surface format to the enum SURFACE_PIXEL_FORMAT_SUBSAMPLE_END since it's not a real format. Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add dsc mst stream pbn log for debugHersen Wu2022-02-161-0/+1
| | | | | | | | | | | | | | | | | | [why] payload and slot number of display on dsc mst hub will be adjusted when there is change on any display on dsc hub. to monitor dsc enable/disable, pbn change, we need add log. [How] add mst_pbn to dc_dsc_config of dc_crtc_timing. add dsc, pbn, display name within dc_core_enable_stream, dc_core_disable_stream, dc_stream_log Reviewed-by: Jerry Zuo <Jerry.Zuo@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Hersen Wu <hersenwu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DP-HDMI FRL PCON Support in DCFangzhi Zuo2021-12-011-0/+3
| | | | | | | | | | | | | | Change since v1: add brief description 1. Add hdmi frl pcon support to existing asic family. 2. Determine pcon frl capability based on pcon dpcd. 3. pcon frl is taken into consideration into mode validation. v2: squash in warning fix (Alex) Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add support for SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616.Mario Kleiner2021-05-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the necessary format definition, bandwidth and pixel size mappings, prescaler setup, and pixelformat selection, following the logic already present for SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616. The new SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 is implemented as the old SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 format, but with swapped red <-> green color channel, by use of the hardware xbar. Please note that on the DCN 1/2/3 display engines, the pixelformat in hubp and dpp setup for the old SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and the new SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 was changed from format id 22 to id 26. See amd/include/navi10_enum.h for the meaning of the id's. For format 22, the display engine read the framebuffer in 16 bpc format, but truncated to the 12 bpc actually supported by later pipeline stages. However, the engine took the 12 LSB of each color component for truncation, which is incompatible with rendering at least under Vulkan, where content is 16 bit wide, and a 12 MSB alignment would be appropriate, if any. Format 20 for ARGB16161616_12MSB does work, but even better, we can choose format 26 for ARGB16161616_UNORM, keeping all 16 bits around until later stages of the display pipeline. This allows to directly consume what the rendering hw produces under Vulkan for swapchain format VK_FORMAT_R16G16B16A16_UNORM, as tested with a patched version of the current AMD open-source amdvlk driver which maps swapchain format VK_FORMAT_R16G16B16A16_UNORM onto DRM_FORMAT_XBGR16161616. The old id 22 would cause colorful pixeltrash to be displayed instead. Tested under DCN-1.0 and DCE-11.2. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add dsc stream overhead for dp onlyWenjing Liu2021-05-101-0/+1
| | | | | | | | | | | | | | | [why] Based on hardware team recommendation this additional dsc overhead is only required for DP DSC. [how] Add a check for is_dp and only apply the overhead if this flag is set. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Increase precision for bpp in DSC calculationsJun Lei2021-03-231-0/+1
| | | | | | | | | | | | | | | [Why?] Many DSC variables and related functions use whole bits for bpp. [How?] Change variables and related functions to use 16ths of a bit for bpp. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Synchronize displays with different timingsVladimir Stempen2021-02-221-0/+1
| | | | | | | | | | | | | | | [why] Vendor based fan noise improvement [how] Report timing synchronizable when DP streams time frame difference is less than 0.05 percent. Adjust DP DTOs and sync displays using MASTER_UPDATE_LOCK_DB_X_Y Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: revert support for DID2.0 dsc passthroughJun Lei2021-02-091-1/+0
| | | | | | | | | | 3x4K60 displays over MST with DSC enabled was not able to light up due to this patch. Signed-off-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: implement support for DID2.0 dsc passthroughJun Lei2021-02-021-0/+1
| | | | | | | | | | | | | | | | | | | [Why] Some panels contain active converters (e.g. DP to MIPI) which only support restricted DSC configurations. DID2.0 adds support for such displays to explicitly define per timing BPP restrictions on DSC. Ignoring these restrictions leads to blackscreen. [How] Add parsing in DID2.0 parser to get this bpp info. Add support in DSC module to constraint target bpp based on this info. Signed-off-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Update idle optimization handlingJoshua Aberback2021-01-051-0/+1
| | | | | | | | | | | | [How] - use dc interface instead of hwss interface in cursor functions, to keep dc->idle_optimizations_allowed updated - add dc interface to check if idle optimizations might apply to a plane Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher2020-11-041-18/+0
| | | | | | | | | | Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Implement AMD VSIF V3Reza Amini2020-07-211-0/+7
| | | | | | | | | | | | | [Why] To support V3 [How] Generate new VSIF for V3 Signed-off-by: Reza Amini <Reza.Amini@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DCN3 Support in DM (v2)Bhawanpreet Lakha2020-07-011-0/+1
| | | | | | | | | Handle DCN3 in amdgpu_dm v2: fix num_pkrs handling Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DCN3 HWSEQBhawanpreet Lakha2020-07-011-0/+3
| | | | | | | Add HW sequence programing for DCN3 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DCN3 MMHUBHUBBhawanpreet Lakha2020-07-011-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to program the DCN3 MMHUBBUB (Multimedia HUB interface) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DCN3 HUBPBhawanpreet Lakha2020-07-011-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to program the DCN3 HUBP (Display to data fabric interface pipe) HW Blocks: +--------++------+ | HUBBUB || HUBP | +--------++------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Make cursor source translation adjustment optionalNicholas Kazlauskas2020-04-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] In some usecases, like tiled display, the stream and plane configuration can be setup in a way where the caller expects DAL to perform the clipping, eg: P0: src_rect(0, 0, w, h) dst_rect(0, 0, w, h) P1: src_rect(w, 0, w, h) dst_rect(0, 0, w, h) Cursor is enabled on both streams with the same position. This can result in double cursor on tiled display, even though this behavior is technically correct from the DC interface point of view. We need a mechanism to control this dynamically. [How] This is something that should live in the DM layer based on detection of the specified configuration but it's not something that we really have enough information to deal with today. Add a flag to the cursor position state that specifies whether we want DC to do the translation or not and make it opt-in and let the DM decide when to do it. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Drop AMD_EDID_UTILITY definesHarry Wentland2019-12-021-8/+0
| | | | | | | | We don't use this upstream in the Linux kernel. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTEDBhawanpreet Lakha2019-11-131-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] DCN2 and DSC are stable enough to be build by default. So drop the flags. [How] Remove them using the unifdef tool. The following commands were executed in sequence: $ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' In addition: * Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup NV defninitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN2 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * dce/dce_dmcu.c: dcn20_*lock_phy() * dce/dce_dmcu.c: dcn20_funcs * dce/dce_dmcu.c: dcn20_dmcu_create() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init() Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Added pixel dynamic expansion control.Robin Singh2019-10-101-0/+5
| | | | | | | | | | | | | | | | | | | [Why] To compare the crc of the framebuffer data at input of display pipeline with the crc of the otg, we need to disable pixel formatter's dynamic expansion feature during crc capture and keep it enable in the normal operation. [HOW] Expose a new interface in DM and dc for pixel formatter (fmt dynamic bitdepth expansion control). Interface control the FMT_DYNAMIC_EXP_EN bit, during crc capture keep it disabled. Signed-off-by: Robin Singh <robin.singh@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Isolate DSC module from driver dependenciesBayan Zabihiyan2019-09-131-24/+33
| | | | | | | | | | | | | | | | | | [Why] Edid Utility wishes to include DSC module from driver instead of doing it's own logic which will need to be updated every time someone modifies the driver logic. [How] Modify some functions such that we dont need to pass the entire DC structure as parameter. -Remove DC inclusion from module. -Filter out problematic types and inclusions Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: remove temporary transition codeDmytro Laktyushkin2019-09-131-29/+0
| | | | | | | | | | Remove code used to allow compilation error free interface change. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Expose OTG_V_TOTAL_MID for HW DiagsBayan Zabihiyan2019-08-231-0/+2
| | | | | | | | | | | | | | | | | | | [Why] Existing HW Features, HW Diags test requested that the registers be exposed. [How] Add V_TOTAL_MID to existing DC structures. Make sure values are passed down throughout DC Add Register definition. Program the additional registers Add additional Logic for V_TOTAL_CONTROL. Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add Cursor Degamma logic for DCN2Bayan Zabihiyan2019-08-231-1/+2
| | | | | | | | | | | | | | [Why] We need to have the ability to to tell us set degamma on the cursor. [How] Pass a flag down to register programming that tells us if the current surface format needs cursor degamma. Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add dcc programming for dual planeDmytro Laktyushkin2019-07-181-28/+26
| | | | | | | | | | | | | | | | | | | Add dual plane dcc programming support for surfaces. Removes unions from plane size and dcc params as they serve no practical purpose only making our code more convoluted. This results in easy dual plane dcc and surface size programming. Temporary diags_dm code is used to handle the interface change without breaking functionality as a diags change needs to be applied after this one. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Implement DAL3 GPU Integer ScalingReza Amini2019-07-181-0/+1
| | | | | | | | | | | | | | | | [WHY] Users want to not have filtering when scaling by integer multiples to native timing. [HOW] If timing is a multiple integer of view, we set number of taps to 1 (effectivly closest neighbour). Signed-off-by: Reza Amini <Reza.Amini@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Optimize gamma calculationsKrunoslav Kovac2019-07-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | [Why&How] 1. Stack usage is pretty high as fixed31_32 struct is 8 bytes and we have functions with >30 vars on the stack. 2. Optimize gamma calculation by reducing number of calls to dc_fixpt_pow Our X points are divided into 32 regions wth 16 pts each. Each region is 2x the previous, meaning x[i] = 2*x[i-16] for i>=16. Using (2x)^gamma = 2^gamma * x^gamma, we can recursively compute powers of gamma, we just need first 16 pts to start it up. dc_fixpt_pow() is expensive, it computes x^y by doing exp(y*logx) Exp is done by Taylor series approximation, and log by Newton-like approximation that also uses exp internally. In short, it's significantly heavier than run-of-the-mill addition/subtraction/multiply. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: move vmid determination logic to a moduleDmytro Laktyushkin2019-06-221-0/+2
| | | | | | | | | | | | | | Currently vmid is decided internally inside dc. With the introduction of new asics we are required to coordinate vmid use with external components. This change converts vmid logic to a DAL module allowing vmid to be passed in as a parameter to DC. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: move DWB structs and enums to dc_hw_typesTyler DiBattista2019-06-221-0/+10
| | | | | | | | | | | [Why] these enums/structs will be used more generically in the future so moving it to dc_hw_types and dc_types Signed-off-by: Tyler DiBattista <tyler.dibattista@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DSC support for Navi (v2)Harry Wentland2019-06-221-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for DCN2 DSC (Display Stream Compression) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ +-------+ | | OPP | <--> | DSC | | +-------+ +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ v2: rebase (Alex) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DCN2 MPCHarry Wentland2019-06-211-1/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to program the DCN2 MPC (Multiple pipe and plane combine) HW Blocks: +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Revert "drm/amd/display: move vmid determination logic out of dc"Alex Deucher2019-06-201-2/+0
| | | | | | | | This reverts commit 11cd74cdb98aa6f4d6f54a0082dd28e0d4743746. Revert this to apply the version that includes DCN2 support. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Gamma logic limitations causing unintended use of RAM over ROM.Harmanprit Tatla2019-06-111-0/+4
| | | | | | | | | | | | | | | | | | | | | [Why] Our existing logic in deciding whether to use RAM or ROM depends on whether we are dealing with an identity gamma ramp. [How] In addition to the is_identity flag a new is_logical_identity flag has been added. The is_identity flag now denotes whether the OS gamma is an RGB256 identity and the new logical identity will inidicate that the given gamma ramp regardless of its type is identity. Signed-off-by: Harmanprit Tatla <harmanprit.tatla@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: move vmid determination logic out of dcDmytro Laktyushkin2019-06-111-0/+2
| | | | | | | | | | | | | Currently vmid is decided internally inside dc. This makes it difficult to use vmid use with external components. This change moves vmid logic outside dc and allowing vmid to be passed in as a parameter to DC. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: color space ycbcr709 supportCharlene Liu2019-05-241-0/+1
| | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Duke Du <Duke.Du@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Introduce DC VM interfaceEryk Brol2019-01-251-0/+2
| | | | | | | | | | | | | | Virtual memory allows display to support flipping to surfaces which are not allocated contiguously in memory with physical addresses, instead a 1-4 level page table is used. This is beneficial because it allows the scattering of large surfaces to improve memory efficiency and security. Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Use 100 Hz precision for pipe pixel clocksKen Chalmers2019-01-141-1/+1
| | | | | | | | | | | | | | | [Why] Users would like more accurate pixel clocks, especially for fractional "TV" frame rates like 59.94 Hz. [How] Store and communicate pixel clocks with 100 Hz accuracy from dc_crtc_timing through to BIOS command table setpixelclock call. Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: move AYCrCb8888 format to video sectionDmytro Laktyushkin2018-12-181-1/+1
| | | | | | | | | | This is a dual channel format and should be treated like other video formats Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Re-arrange GFX9 fieldsNevenko Stupar2018-11-301-3/+4
| | | | | | | | | For more clear usage in future Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Calculate swizzle mode using bpp during validationSu Sung Chung2018-10-091-1/+2
| | | | | | | | | | | | | | | | | | | | [Why] Previously bandwidth validation was failing because swizzle mode was not initialized during plane_state allocation. The swizzle mode was calculated using pixed format which is how swizzle mode is initially calculated in addrlib. [How] * Set default swizzle mode for validation to DC_SW_UNKNOWN * Created new function in dcn10_assign_swizzle_mode which sets the plane swizzle mode based on selected pixed format * Added the call of assign_swizzle_mode into dc_validate_global_state * Set failsafe swizzle mode back to DC_SW_LINEAR Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Refactor FreeSync moduleAnthony Koo2018-08-271-6/+0
| | | | | | | | | | | Remove dependency on internal sink map and instead use existing stream and plane state Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-31 17:55:47 +0000