summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/display/dc/dcn21
Commit message (Expand)AuthorAgeFilesLines
* drm/amd/display: Fix memory leak in dcn21_clock_source_createMiaoqian Lin2022-04-211-0/+1
* drm/amdgpu/display: change pipe policy for DCN 2.1Benjamin Marty2022-04-061-1/+1
* drm/amd/display: move FPU operations from dcn21 to dml/dcn20 folderMelissa Wen2022-03-153-581/+25
* drm/amd/display: move FPU-related code from dcn20 to dml folderMelissa Wen2022-03-151-1/+7
* drm/amd/display: Changed pipe split policy to allow for multi-display pipe splitAngus Wang2021-12-301-1/+1
* drm/amd/display: fix function scopesIsabella Basso2021-12-134-30/+27
* drm/amd: append missing includesIsabella Basso2021-12-131-0/+2
* drm/amd/display: Add DP-HDMI FRL PCON Support in DCFangzhi Zuo2021-12-011-0/+2
* drm/amd/display: Re-arrange FPU code structure for dcn2xQingqing Zhuo2021-10-061-1/+1
* drm/amd/display: Move specific DCN2x code that uses FPU to DMLRodrigo Siqueira2021-08-051-0/+2
* drm/amd/display: Add missing DCN21 IP parameterVictor Lu2021-07-271-0/+1
* drm/amd/display: Enable eDP ILR on DCN2.1Michael Strauss2021-07-231-1/+2
* drm/amd/display: log additional register state for debugJosip Pavic2021-07-213-2/+15
* drm/amd/display: Add interface for ADD & DROP PIXEL RegistersWesley Chalmers2021-06-082-2/+4
* drm/amd/display: Add Interface to set FIFO ERRDET SW OverrideWesley Chalmers2021-06-081-0/+1
* drm/amd/display: Revert "Fix clock table filling logic"Ilya Bakoulin2021-06-081-21/+12
* drm/amd/display: Refactor visual confirmWyatt Wood2021-06-081-2/+1
* Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue"Qingqing Zhuo2021-05-271-1/+0
* drm/amd/display: Refactor and add visual confirm for HW Flip QueueWyatt Wood2021-05-191-0/+1
* drm/amd/display: Fix clock table filling logicIlya Bakoulin2021-05-101-12/+21
* drm/amd/display: Added multi instance support for ABMJake Wang2021-04-281-1/+1
* drm/amd/display: Added support for multiple eDP BL controlJake Wang2021-04-151-0/+2
* drm/amd/display: Add function and debugfs to dump DCC_EN bitVictor Lu2021-04-091-1/+2
* drm/amd/display: revert max lb lines changeDmytro Laktyushkin2021-04-091-1/+1
* drm/amd/display: hide VGH asic specific structsDmytro Laktyushkin2021-04-091-1/+0
* drm/amd/display: Separate caps for maximum RGB and YUV plane countsAtufa Khan2021-03-231-0/+2
* drm/amd/display: use max lb for latency hidingDmytro Laktyushkin2021-03-231-3/+6
* drm/amd/display: remove duplicate include in dcn21 and gpioZhang Yunkai2021-03-231-1/+0
* drm/amd/display: Revert dram_clock_change_latency for DCN2.1Sung Lee2021-03-231-1/+1
* drm/amd/display: Enable pflip interrupt upon pipe enableQingqing Zhuo2021-03-231-0/+1
* drm/amdgpu/display: use GFP_ATOMIC in dcn21_validate_bandwidth_fp()Holger Hoffstätte2021-03-051-1/+1
* drm/amd/display: Fix nested FPU context in dcn21_validate_bandwidth()Holger Hoffstätte2021-03-051-4/+0
* drm/amd/display: Old sequence for HUBP blankAurabindo Pillai2021-02-181-1/+0
* drm/amd/display: Copy over soc values before bounding box creationSung Lee2021-02-181-0/+5
* drm/amd/display: Populate dcn2.1 bounding box before state duplicationSung Lee2021-02-181-2/+2
* drm/amd/display: Add FPU wrappers to dcn21_validate_bandwidth()Jan Kokemüller2021-02-181-2/+18
* drm/amd/display: Initialize dmub_rb_cmd unions to 0Wyatt Wood2021-02-091-1/+3
* drm/amd/display: Add more Clock Sources to DCN2.1Sung Lee2021-02-021-0/+10
* drm/amd/display: Update dram_clock_change_latency for DCN2.1Jake Wang2021-01-201-1/+1
* drm/amd/display: New sequence for HUBP blankWesley Chalmers2021-01-131-0/+1
* drm/amdgpu/display: drop DCN support for aarch64Alex Deucher2021-01-051-4/+0
* drm/amd/display: Adding prototype for dccg21_update_dpp_dto()Souptick Joarder2020-12-151-0/+1
* drm/amd/display: Revert DCN2.1 dram_clock_change_latency updateMichael Strauss2020-12-081-1/+1
* drm/amd/display: Update dram_clock_change_latency for DCN2.1Sung Lee2020-12-011-1/+1
* drm/amd/display: To update backlight restore mechanismCamille Cho2020-11-241-1/+3
* drm/amd/display: Populate hostvm parameter before DML calculationSung Lee2020-11-162-1/+3
* drm/amd/display: cap dpp dto phase not more than modulo.Yongqiang Sun2020-11-101-21/+25
* drm/amd/display: update dpp dto phase and modulo.Yongqiang Sun2020-11-104-2/+164
* drm/amd/display: force use sRGB for video TF is sRGB or BT709Jing Zhou2020-11-101-0/+1
* drm/amd/display: Prevent freesync power optimization during validationIsabel Zhang2020-11-101-10/+18
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-13 07:33:26 +0000