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path: root/drivers/gpu/drm/amd/display/dc/link/protocols
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* drm/amd/display: Restructure dpia link trainingPeichen Huang2024-09-185-46/+154
| | | | | | | | | | | | | | | | | | | | | | | [WHY] We intend to consolidate dp tunneling and conventional dp link training. [HOW] 1. Use the same link training entry for both dp and dpia 2. Move SET_CONFIG of non-transparent mode to dmub side 3. Add set_tps_notification dmub_cmd to notify tps request for non-transparent dpia link training 4. Check dpcd request result and abort link training early if dpia aux tunneling fails 5. Add option to avoid affect old product 6. Separately handle wait_time_microsec for dpia Reviewed-by: Cruise Hung <cruise.hung@amd.com> Reviewed-by: George Shen <george.shen@amd.com> Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Implement new DPCD register handlingRyan Seto2024-09-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | [WHY] There are some monitor timings that seem to be supported without DSC but actually require DSC to be displayed. A VESA SCR introduced a new max uncompressed pixel rate cap register that we can use to handle these edge cases. [HOW] SST: Read caps from link and invalidate timings that exceed the max limit but do not support DSC. Then check for options override when determining BPP. MST: Read caps from virtual DPCD peer device or daisy chained SST monitor and set validation set BPPs to max if pixel rate exceeds uncompressed limit. Validation set optimization continues as normal. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Ryan Seto <ryanseto@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Support UHBR10 link rate on eDPSung Joon Kim2024-08-201-0/+3
| | | | | | | | | | | | | | | | | | [why] Supporting UHBR10 link rate on eDP leverages the existing DP2.0 code but need to add some small adjustments in code. [how] Acknowledge the given DPCD caps for UHBR10 link rate support and allow DP2.0 programming sequence and link training for eDP. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Sung Joon Kim <Sungjoon.Kim@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Allow UHBR Interop With eDP Supported Link Rates TableMichael Strauss2024-08-203-33/+39
| | | | | | | | | | | | | | | | | | | | [WHY] eDP 2.0 is introducing support for UHBR link rates, however current eDP ILR link optimization does not account for UHBR capabilities. Either UHBR capabilities will be provided via the same 128b/132b rate DPCD caps that are currently used on DP2.1, or Table 4-13 may be updated to include UHBR rates. [HOW] Add extra Supported Link Rates table translations for UHBR10/13.5/20. Update eDP link setting optimization search to be aware of 128b/132b DPCD rate caps in order to unblock UHBR on panels with Supported Link Rates table. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Print Pcon FRL Link BW in Debug MessageFangzhi Zuo2024-08-061-0/+2
| | | | | | | | | | | | | | | Under autonomous mode, source reads dpcd DP_PCON_HDMI_POST_FRL_STATUS for the frl link status. Without dsc passthrough, it serves as bw bottleneck on the entire link, compared with the dp link from source to the converter where dsc is available. Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Check null pointers before usedAlex Hung2024-07-231-1/+1
| | | | | | | | | | | | | | | [WHAT & HOW] Poniters, such as dc->clk_mgr, are null checked previously in the same function, so Coverity warns "implies that "dc->clk_mgr" might be null". As a result, these pointers need to be checked when used again. This fixes 10 FORWARD_NULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Replace assert with error message in dp_retrieve_lttpr_cap()Roman Li2024-07-231-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | [Why] When assert in dp_retrieve_lttpr_cap() is hit, dmesg has traces like: RIP: 0010:dp_retrieve_lttpr_cap+0xcc/0x1a0 [amdgpu] Call Trace: <TASK> dp_retrieve_lttpr_cap+0xcc/0x1a0 [amdgpu] report_bug+0x1e8/0x240 handle_bug+0x46/0x80 link_detect+0x35/0x580 [amdgpu] It happens when LTTPRs fail to increment dpcd repeater count. We have a recovery action in place for such cases. Assert is misleading, an indicative error in dmesg is more useful. [How] Remove ASSERT and use DC_LOG_ERROR instead. Reviewed-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix possible overflow in integer multiplicationAlex Hung2024-07-011-1/+1
| | | | | | | | | | | | | | | [WHAT & HOW] Integer multiplies integer may overflow in context that expects an expression of unsigned/siged long long (64 bits). This can be fixed by casting integer to unsigned/siged long long to force 64 bits results. This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Validate function returnsAlex Hung2024-06-271-2/+1
| | | | | | | | | | | | | [WHAT & HOW] Function return values must be checked before data can be used in subsequent functions. This fixes 4 CHECKED_RETURN issues reported by Coverity. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix reduced resolution and refresh rateDaniel Sa2024-06-271-10/+11
| | | | | | | | | | | | | | | | | | | | [WHY] Some monitors are forced to a lower resolution and refresh rate after system restarts. [HOW] Some monitors may give invalid LTTPR information when queried such as indicating they have one DP lane instead of 4. If given an invalid DPCD version, skip over getting lttpr link rate and lane counts. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Daniel Sa <daniel.sa@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Send DP_TOTAL_LTTPR_CNT during detection if LTTPR is presentMichael Strauss2024-06-271-1/+9
| | | | | | | | | | | | | | | | | [WHY] New register field added in DP2.1 SCR, needed for auxless ALPM [HOW] Echo value read from 0xF0007 back to sink Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Revert "drm/amd/display: workaround for oled eDP not lighting up on DCN401"Joshua Aberback2024-06-141-3/+0
| | | | | | | | | | | | This reverts commit e902dd7f3e3b93a401e1d3c0322cce933e75e809. A proper fix for this issue has been implemented in DMUB FW. So, no need to keep the workaround. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Remove reduntant comparisons by CoverityIvan Lipski2024-06-141-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] Coverity analysis of the Upstream display driver code (amd-staging-drm-next) flagged these three functions as containing 'CONSTANT_EXPRESSION_RESULT' errors, i. e. the conditionals are reduntant since their result is predetermined. fixpt31_32.c: The two flagged 'ASSERT' lines redundant since they are always true: - LONG_MAX equals to the largest 'signed long long' number - res.value is type 'signed long long', So, the condition inside the 'ASSERTS's is always link_dp_training.c: The flagged conditional statement is always false: - 'max_requested.FFE_PRESET.settings.level' is 4 bits, so its max possible value is 15 - 'DP_FFE_PRESET_MAX_LEVEL' equals to 15. So, the conditional statement is always false and the wrapped code never executes. [HOW] Removed lines flagged by Coverity analysis. Reviewed-by: Sun peng Li <sunpeng.li@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Ivan Lipski <ivlipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Revert "drm/amd/display: Handle HPD_IRQ for internal link"Sung-huai Wang2024-06-141-15/+9
| | | | | | | | | | | | | [How&Why] This reverts commit 239b31bd5c3fef3698440bf6436b2068c6bb08a3. Due to the it effects Replay resync. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Sung-huai Wang <danny.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: use preferred link settings for dp signal onlyWenjing Liu2024-06-141-14/+10
| | | | | | | | | | | | | [why] We set preferred link settings for virtual signal. However we don't support virtual signal for UHBR link rate. If preferred is set to UHBR link rate, we will allow virtual signal with UHBR link rate which causes system crashes. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Ignore UHBR13.5 cable ID cap for passive cable max link rateGeorge Shen2024-06-141-1/+2
| | | | | | | | | | | | | | | | [Why] Passive DP40 cables were updated in the latest DP spec to support UHBR13.5 link rate. Current max link rate logic checks against the cable ID DPCD even for passive cables. [How] Ignore UHBR13.5 cable ID DPCD cap in get_max_link_rate logic. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add fallback defaults for invalid LTTPR DPCD capsMichael Strauss2024-06-141-3/+16
| | | | | | | | | | | | | | | | | [WHY] Some sinks are observed to return invalid LTTPR revision and/or invalid LTTPR link rate capabilities. [HOW] Assume any LTTPR which reports invalid max link rate supports HBR3. Don't validate LTTPR DPCD revision in dp_is_lttpr_present check. Reviewed-by: George Shen <george.shen@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Extend PSRSU residency modeJack Chang2024-06-142-3/+3
| | | | | | | | | | 1. To support multiple PSRSU residency measurement mode Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Jack Chang <jack.chang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add retires when read DPCDJoan Lee2024-06-051-6/+20
| | | | | | | | | | | | [why & how] Sometimes read DPCD return fail while result not retrieved yet. Add retries mechanism in Replay handle hpd irq to get real result. Reviewed-by: Jerry Zuo <jerry.zuo@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Joan Lee <joan.lee@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: workaround for oled eDP not lighting up on DCN401Joshua Aberback2024-06-051-0/+3
| | | | | | | | | | | | | | | | | | [Why] Currently there's an issue on DCN401 that prevents oled eDP panels from being lit up that is still under investigation. To unblock dev work while investigating, we can work around the issue by skipping toggling the enablement of the backlight. [How] - new debug bit that will skip touching backlight enable DPCD for oled Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: turn on symclk for dio virtual stream in dpms sequenceWenjing Liu2024-06-051-0/+3
| | | | | | | | | | | | | | | [why] In order to support glitchless display clock ramping for virtual stream, we must turn on symclk for stream encoder. The code will power on phy and enable symclk for dio encoder during virtual stream dpms sequence. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: remove unused struct 'aux_payloads'Dr. David Alan Gilbert2024-05-201-4/+0
| | | | | | | | | 'aux_payloads' is unused since commit eae5ffa9bd7b ("drm/amd/display: Switch ddc to new aux interface") Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Not fallback if link BW is smaller than req BWCruise2024-05-202-17/+4
| | | | | | | | | | | | | | | | | | | [Why] When the link BW is smaller than the request BW, the DP LT just kept running and fallback to lower link config. DP LT just aborted if is_hpd_pending bit is high. But is_hpd_pending bit indicates a new HPD event received. It doesn't mean the HPD is low. [How] Abort the DP LT if the link BW is smaller than the request BW. Remove checking is_hpd_pending bit in DP LT. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Cruise <cruise.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Check UHBR13.5 cap when determining max link capGeorge Shen2024-05-131-4/+18
| | | | | | | | | | | | | [WHY] UHBR13.5 support is optional, even if UHBR20 is supported by the device. If source supports max UHBR13.5 while sink, cable and LTTPR support UHBR20 but not UHBR13.5, UHBR10 should be used as the max link cap. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Expand to higher link ratesSung Joon Kim2024-05-131-0/+3
| | | | | | | | | | | | [WHY & HOW] To support higher link rates that sink allows, we need to make sure driver is ready and perform correct link-training sequence. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix Coverity INTEGER_OVERFLOW within ↵Hersen Wu2024-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | decide_fallback_link_setting_max_bw_policy [Why] For addtion (uint8_t) variable + constant 1, coverity generates message below: Truncation due to cast operation on "cur_idx + 1" from 32 to 8 bits. Then Coverity assume result is 32 bits value be saved into 8 bits variable. When result is used as index to access array, Coverity suspects index invalid. [How] Change varaible type to uint32_t. Reviewed-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add missing NULL pointer check within dpcd_extend_address_rangeHersen Wu2024-05-021-0/+1
| | | | | | | | | | | | [Why & How] ASSERT if return NULL from kcalloc. Reviewed-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Check index for aux_rd_interval before usingAlex Hung2024-05-021-2/+2
| | | | | | | | | | | | aux_rd_interval has size of 7 and should be checked. This fixes 3 OVERRUN and 1 INTEGER_OVERFLOW issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix FEC_READY write on DP LTIlya Bakoulin2024-04-301-8/+6
| | | | | | | | | | | | | | | | [Why/How] We can miss writing FEC_READY in some cases before LT start, which violates DP spec. Remove the condition guarding the DPCD write so that the write happens unconditionally. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Disable error correction if it's not supportedCruise2024-04-301-26/+21
| | | | | | | | | | | | | | [Why] Error correction was enabled in a monitor which doesn't support. [How] Disable error correction if it's not supported Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Cruise <cruise.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Allocate zero bw after bw alloc enableMeenakshikumar Somasundaram2024-04-301-1/+9
| | | | | | | | | | | | | | | | | | | | [Why] During DP tunnel creation, CM preallocates BW and reduces estimated BW of other DPIA. CM release preallocation only when allocation is complete. Display mode validation logic validates timings based on bw available per host router. In multi display setup, this causes bw allocation failure when allocation greater than estimated bw. [How] Do zero alloc to make the CM to release preallocation and update estimated BW correctly for all DPIAs per host router. Reviewed-by: PeiChen Huang <peichen.huang@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Handle HPD_IRQ for internal linkSung-huai Wang2024-04-301-9/+16
| | | | | | | | | | | | | | | | [Why] TCON data is corrupted after electro static discharge test. Once the TCON data get corrupted, they will get themselves reset and send HPD_IRQ to source side. [How] Support HPD_IRQ for internal link, and restore the PSR/Replay setup. Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Sung-huai Wang <danny.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix uninitialized variables in DCAlex Hung2024-04-261-1/+1
| | | | | | | | | This fixes 29 UNINIT issues reported by Coverity. Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix uninitialized variables in DCAlex Hung2024-04-264-16/+16
| | | | | | | | | This fixes 49 UNINIT issues reported by Coverity. Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Change DPCD address rangeRodrigo Siqueira2024-04-121-1/+1
| | | | | | | | | Change DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT with DP_PHY_REPEATER_128B132B_RATES. Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix compiler warnings on high compiler warning levelsAric Cyr2024-04-091-2/+2
| | | | | | | | | | | | | | | | [why] Enabling higher compiler warning levels results in many issues that can be trivially resolved as well as some potentially critical issues. [how] Fix all compiler warnings found with various compilers and higher warning levels. Primarily, potentially uninitialized variables and unreachable code. Reviewed-by: Leo Li <sunpeng.li@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: handle invalid connector indicesJoshua Aberback2024-04-091-2/+2
| | | | | | | | | | | | | | | | | | | [Why] The function to count the number of valid connectors does not guarantee that the first n indices are valid, only that there exist n valid indices. When invalid indices are present, this results in later valid connectors being missed, as processing would end after checking n indices. [How] - count valid indices separately from total indices examined - add explicit definition of MAX_LINKS Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Expand supported Replay residency modeLeon Huang2024-04-092-3/+6
| | | | | | | | | | | | | | | | [Why] Dmub provides several Replay residency calculation methods, but current interface only supports either ALPM or PHY mode [How] Modify the interface for supporting different types of Replay residency calculation. Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Leon Huang <leon.huang1@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Enable new interface design for alternate scramblingSung Joon Kim2024-03-223-15/+67
| | | | | | | | | | | | [why & how] To enable a new interface so alternate scrambling can be done via security module. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Amend coasting vtotal for replay low hzChunTao Tso2024-03-202-4/+4
| | | | | | | | | | | | | | | | | | [WHY] The original coasting vtotal is 2 bytes, and it need to be amended to 4 bytes because low hz case. [HOW] Amend coasting vtotal from 2 bytes to 4 bytes. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: ChunTao Tso <chuntao.tso@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Use kcalloc() instead of kzalloc()Lenko Donchev2024-02-221-1/+1
| | | | | | | | | | | | | | | We are trying to get rid of all multiplications from allocation functions to prevent integer overflows. Here the multiplication is obviously safe, but using kcalloc() is more appropriate and improves readability. This patch has no effect on runtime behavior. Link: https://www.kernel.org/doc/html/next/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments Link: https://github.com/KSPP/linux/issues/162 Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Lenko Donchev <lenko.donchev@gmail.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add 'replay' NULL check in 'edp_set_replay_allow_active()'Srinivasan Shanmugam2024-02-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the first if statement, we're checking if 'replay' is NULL. But in the second if statement, we're not checking if 'replay' is NULL again before calling replay->funcs->replay_set_power_opt(). if (replay == NULL && force_static) return false; ... if (link->replay_settings.replay_feature_enabled && replay->funcs->replay_set_power_opt) { replay->funcs->replay_set_power_opt(replay, *power_opts, panel_inst); link->replay_settings.replay_power_opt_active = *power_opts; } If 'replay' is NULL, this will cause a null pointer dereference. Fixes the below found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_edp_panel_control.c:895 edp_set_replay_allow_active() error: we previously assumed 'replay' could be null (see line 887) Fixes: c7ddc0a800bc ("drm/amd/display: Add Functions to enable Freesync Panel Replay") Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Suggested-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Update FIXED_VS Retimer HWSS Test Pattern SequencesMichael Strauss2024-02-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] Need to fix some broken logic and sequencing in initial commit [HOW] Fix logic handling override deprogramming when exiting SQ128. Don't exit early from dp_set_hw_lane_settings for DP2/FIXED_VS case. Move LTTPR 128b/132b check out of requires_hwss and check during runtime, as LTTPR caps are not populated on initial call. Add pending_test_pattern to link state to allow HWSS to set FFE overrides on retimer TX and/or skip setting APU TX FFE depending on requested pattern. Use updated clock source for SQ128 override sequence. Skip HW FFE preset programming when performing test pattern overrides. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add align done checkZhikai Zhai2024-02-141-1/+4
| | | | | | | | | | | | | | | | | | [WHY] We Double-check link status if training successful, but miss the lane align status. [HOW] Add the lane align status check Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Zhikai Zhai <zhikai.zhai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Initialize 'wait_time_microsec' variable in ↵Srinivasan Shanmugam2024-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | link_dp_training_dpia.c wait_time_microsec = max(wait_time_microsec, (uint32_t) DPIA_CLK_SYNC_DELAY); Above line is trying to assign the maximum value between 'wait_time_microsec' and 'DPIA_CLK_SYNC_DELAY' to wait_time_microsec. However, 'wait_time_microsec' has not been assigned a value before this line, initialize 'wait_time_microsec' at the point of declaration. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_dpia.c:697 dpia_training_eq_non_transparent() error: uninitialized symbol 'wait_time_microsec'. Fixes: 630168a97314 ("drm/amd/display: move dp link training logic to link_dp_training") Cc: Wenjing Liu <wenjing.liu@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: correct comment in set_default_brightness_aux()Camille Cho2024-02-071-1/+1
| | | | | | | | | 0 nits is a valid default value for OLED panels. So, update the relevant comment to account for that fact. Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Signed-off-by: Camille Cho <camille.cho@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Don't perform rate toggle on DP2-capable FIXED_VS retimersMichael Strauss2024-02-071-10/+12
| | | | | | | | | | | | | [WHY] Only required if FIXED_VS retimer does not support DP2-capable. [HOW] Gate link rate toggle with DP 128b/132b LTTPR channel coding cap check. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Remove Legacy FIXED_VS Transparent LT SequenceMichael Strauss2024-02-073-359/+1
| | | | | | | | | | | | The New sequence has been in use in DCN314 with no regressions introduced. Therefore, it is safe to enable this sequence for all devices using FIXED_VS retimers. So, remove the legacy codepath and its associated config flag. Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix buffer overflow in 'get_host_router_total_dp_tunnel_bw()'Srinivasan Shanmugam2024-01-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The error message buffer overflow 'dc->links' 12 <= 12 suggests that the code is trying to access an element of the dc->links array that is beyond its bounds. In C, arrays are zero-indexed, so an array with 12 elements has valid indices from 0 to 11. Trying to access dc->links[12] would be an attempt to access the 13th element of a 12-element array, which is a buffer overflow. To fix this, ensure that the loop does not go beyond the last valid index when accessing dc->links[i + 1] by subtracting 1 from the loop condition. This would ensure that i + 1 is always a valid index in the array. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_dpia_bw.c:208 get_host_router_total_dp_tunnel_bw() error: buffer overflow 'dc->links' 12 <= 12 Fixes: 59f1622a5f05 ("drm/amd/display: Add dpia display mode validation logic") Cc: PeiChen Huang <peichen.huang@amd.com> Cc: Aric Cyr <aric.cyr@amd.com> Cc: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix uninitialized variable usage in core_link_ 'read_dpcd() ↵Srinivasan Shanmugam2024-01-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | & write_dpcd()' functions The 'status' variable in 'core_link_read_dpcd()' & 'core_link_write_dpcd()' was uninitialized. Thus, initializing 'status' variable to 'DC_ERROR_UNEXPECTED' by default. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dpcd.c:226 core_link_read_dpcd() error: uninitialized symbol 'status'. drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dpcd.c:248 core_link_write_dpcd() error: uninitialized symbol 'status'. Cc: stable@vger.kernel.org Cc: Jerry Zuo <jerry.zuo@amd.com> Cc: Jun Lei <Jun.Lei@amd.com> Cc: Wayne Lin <Wayne.Lin@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-18 12:35:45 +0000