summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/icl_dsi.c
Commit message (Expand)AuthorAgeFilesLines
* drm/i915/icl: Fix port disable sequence for mipi-dsiVandita Kulkarni2019-04-101-1/+1
* drm/i915/icl: Ungate ddi clocks before IO enableVandita Kulkarni2019-04-101-0/+6
* drm/i915/icl: Simplify release of encoder power refsImre Deak2019-04-081-7/+5
* drm/i915: Get power refs in encoder->get_power_domains()Imre Deak2019-04-081-20/+20
* drm/i915: extract intel_panel.h from intel_drv.hJani Nikula2019-04-081-0/+1
* drm/i915: extract intel_connector.h from intel_drv.hJani Nikula2019-04-081-0/+1
* drm/i915: extract intel_ddi.h from intel_drv.hJani Nikula2019-04-081-1/+3
* drm/i915: switch intel_wait_for_register to uncoreDaniele Ceraolo Spurio2019-03-261-2/+4
* drm/i915/cnl: use previous pll hw readoutLucas De Marchi2019-03-261-3/+2
* drm/i915: Adjust DSI fixed mode handlingVille Syrjälä2019-03-221-12/+2
* drm/i915: Make combo PHY DDI macro definitions consistent for ICL and CNLAditya Swarup2019-02-141-4/+4
* drm/i915/backlight: Restore backlight on resume, v3.Maarten Lankhorst2019-01-241-0/+1
* drm/i915: Pass down rc in intel_encoder->compute_config()Lyude Paul2019-01-161-4/+4
* drm/i915: Markup paired operations on display power domainsChris Wilson2019-01-141-12/+24
* drm/i915/icl: add pll mapping for DSIJani Nikula2018-12-031-0/+25
* drm/i915/icl: Ungate DSI clocksMadhav Chauhan2018-12-031-0/+19
* drm/i915/icl: Gate clocks for DSIMadhav Chauhan2018-12-031-0/+20
* drm/i915/icl: Configure DSI Dual link modeMadhav Chauhan2018-12-031-1/+41
* drm/i915/icl: Add DSI encoder compute config hookMadhav Chauhan2018-12-031-0/+31
* drm/i915/icl: Get HW state for DSI encoderMadhav Chauhan2018-12-031-0/+59
* drm/i915/icl: Add get config functionality for DSIVandita Kulkarni2018-12-031-0/+15
* drm/i915/icl: Allocate DSI hosts and imlement host transferMadhav Chauhan2018-12-031-0/+147
* drm/i915/icl: Fill DSI ports infoMadhav Chauhan2018-12-031-0/+8
* drm/i915/icl: Use the same pll functions for dsiVandita Kulkarni2018-12-031-5/+11
* drm/i915/icl: Allocate DSI encoder/connectorMadhav Chauhan2018-12-031-8/+109
* drm/i915/icl: Find DSI presence for ICLMadhav Chauhan2018-11-011-0/+8
* drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registersMadhav Chauhan2018-10-311-0/+52
* drm/i915/icl: Disable DSI IO powerMadhav Chauhan2018-10-311-0/+23
* drm/i915/icl: Disable DSI portsMadhav Chauhan2018-10-311-0/+23
* drm/i915/icl: Disable portsync modeMadhav Chauhan2018-10-311-0/+10
* drm/i915/icl: Disable DDI functionMadhav Chauhan2018-10-311-0/+8
* drm/i915/icl: Put DSI link in ULPSMadhav Chauhan2018-10-311-0/+26
* drm/i915/icl: Power down DSI panelMadhav Chauhan2018-10-311-0/+15
* drm/i915/icl: Disable DSI transcodersMadhav Chauhan2018-10-311-0/+26
* drm/i915/icl: Turn OFF panel backlightMadhav Chauhan2018-10-311-0/+12
* drm/i915/icl: Turn ON panel backlightMadhav Chauhan2018-10-311-0/+6
* drm/i915/icl: Wait for header/payload credits releaseMadhav Chauhan2018-10-311-0/+74
* drm/i915/icl: Power on DSI panelMadhav Chauhan2018-10-311-0/+7
* drm/i915/icl: Set max return packet size for DSI panelMadhav Chauhan2018-10-311-0/+33
* drm/i915/icl: Enable DSI transcodersMadhav Chauhan2018-10-221-0/+25
* drm/i915/icl: Configure DSI transcoder timingsMadhav Chauhan2018-10-221-0/+118
* drm/i915/icl: Program TRANS_DDI_FUNC_CTL registersMadhav Chauhan2018-10-221-4/+60
* drm/i915/icl: Configure DSI transcodersMadhav Chauhan2018-10-221-1/+86
* drm/i915/icl: Get DSI transcoder for a given portMadhav Chauhan2018-10-221-0/+8
* drm/i915/icl: Program TA_TIMING_PARAM registersMadhav Chauhan2018-10-221-0/+21
* drm/i915/icl: Program DSI clock and data lane timing paramsMadhav Chauhan2018-10-221-0/+18
* drm/i915/icl: Program T_INIT_MASTER registersMadhav Chauhan2018-09-241-0/+19
* drm/i915/icl: Enable DDI BufferMadhav Chauhan2018-09-241-0/+22
* drm/i915/icl: DSI vswing programming sequenceMadhav Chauhan2018-09-241-0/+120
* drm/i915/icl: Configure lane sequencing of combo phy transmitterMadhav Chauhan2018-09-241-0/+39
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-12 19:15:48 +0000