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path: root/drivers/gpu/drm/i915/intel_dp.c
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* Revert "drm/i915: Check live status before reading edid"David Weinehall2016-10-311-1/+1
* drm/i915: Only ignore eDP ports that are connectedChris Wilson2016-09-151-6/+6
* drm/i915: Fix hpd live status bits for g4xVille Syrjälä2016-09-151-7/+7
* drm/i915: Revert DisplayPort fast link training featureMika Kahola2016-07-271-26/+2
* drm/i915: Refresh cached DP port register value on resumeVille Syrjälä2016-07-271-3/+5
* drm/i915/ddi: Fix eDP VDD handling during booting and suspend/resumeImre Deak2016-05-111-2/+2
* drm/i915: Clean up AUX power domain handlingVille Syrjälä2015-12-021-34/+14
* drm/i915: Don't override output type for DDI HDMITakashi Iwai2015-11-251-1/+2
* drm/i915: Throw out some useless variablesVille Syrjälä2015-10-131-5/+5
* drm/i915: use error pathSudip Mukherjee2015-10-081-9/+14
* drm/i915: Rename DP link training functionsAnder Conselvan de Oliveira2015-10-061-9/+13
* drm/i915: Don't bypass LRC on CHVVille Syrjälä2015-10-061-5/+0
* drm/i915: make backlight hooks connector specificJani Nikula2015-09-301-1/+1
* drm/i915: Constify adjusted_modeVille Syrjälä2015-09-301-1/+1
* Merge remote-tracking branch 'airlied/drm-next' into drm-intel-nextDaniel Vetter2015-09-301-0/+1
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| * drm/i915: Handle DP_AUX_I2C_WRITE_STATUS_UPDATEVille Syrjälä2015-09-081-0/+1
* | drm/i915: Make sure we don't detect eDP on g4xVille Syrjälä2015-09-231-0/+7
* | drm/i915: Check live status before reading edidSonika Jindal2015-09-231-1/+1
* | drm/i915/skl: handle port E in cpt_digital_port_connectedJani Nikula2015-09-211-0/+3
* | drm/i915/bxt: Use intel_encoder->hpd_pin to check live statusSonika Jindal2015-09-141-3/+6
* | drm/i915: use the yesno helper for loggingJani Nikula2015-09-041-2/+2
* | drm/i915: ignore link rate in TPS3 selectionJani Nikula2015-09-041-3/+4
* | drm/i915/dp: move TPS3 logic to where it's usedJani Nikula2015-09-041-14/+17
* | Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter2015-09-021-30/+45
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| * i915: Set ddi_pll_sel in DP MST pathAnder Conselvan de Oliveira2015-09-011-1/+1
| * drm/i915: Don't use link_bw for PLL setupVille Syrjälä2015-09-011-22/+22
| * drm/i915: eDP can be present on DDI-ERodrigo Vivi2015-08-311-4/+5
| * drm/i915: Check DP link status on long hpd tooVille Syrjälä2015-08-311-6/+5
| * drm/i915/skl: enable DDI-E hotplugXiong Zhang2015-08-261-0/+3
| * drm/i915: fix link rates reported for SKLThulasimani,Sivakumar2015-08-241-8/+11
| * Merge tag 'v4.2-rc8' into drm-nextDave Airlie2015-08-241-13/+22
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| | * drm/i915: Avoid TP3 on CHVThulasimani,Sivakumar2015-08-191-8/+22
| | * drm/i915: remove HBR2 from chv supported listThulasimani,Sivakumar2015-08-191-3/+4
| | * Revert "drm/i915: Add eDP intermediate frequencies for CHV"Thulasimani,Sivakumar2015-08-191-6/+0
* | | drm/i915: move intel_hrawclk() to intel_display.cJani Nikula2015-09-021-34/+0
* | | drm/i915: Clean up CHV lane soft reset programmingVille Syrjälä2015-09-011-43/+48
* | | drm/i915/dp: use the drm dp helper for determining sink tps3 supportJani Nikula2015-09-011-2/+1
* | | drm/i915: Force common lane on for the PPS kick on CHVVille Syrjälä2015-08-261-3/+13
* | | drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä2015-08-261-0/+23
* | | drm/i915: Implement PHY lane power gating for CHVVille Syrjälä2015-08-261-50/+91
* | | drm/i915/bxt: Use correct live status register for BXT platformJani Nikula2015-08-261-0/+25
* | | drm/i915: split g4x_digital_port_connected to g4x and vlv variantsJani Nikula2015-08-261-31/+39
* | | drm/i915: split ibx_digital_port_connected to ibx and cpt variantsJani Nikula2015-08-261-35/+43
* | | drm/i915: add common intel_digital_port_connected functionJani Nikula2015-08-261-19/+22
* | | drm/i915: add MISSING_CASE annotation to ibx_digital_port_connectedJani Nikula2015-08-261-2/+8
* | | drm/i915: make g4x_digital_port_connected return boolean statusJani Nikula2015-08-261-15/+11
* | | drm/i915: move ibx_digital_port_connected to intel_dp.cJani Nikula2015-08-261-8/+53
* | | drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer dis...Ville Syrjälä2015-08-261-0/+23
* | | drm/i915: Always program unique transition scale for CHVVille Syrjälä2015-08-261-27/+26
* | | drm/i915: Put back lane_count into intel_dp and add link_rate tooVille Syrjälä2015-08-261-29/+24
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