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path: root/drivers/gpu/drm/i915/intel_pm.c
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* drm/i915: Downgrade Gen9 Plane WM latency errorChris Wilson2019-05-161-2/+2
* drm/i915: Disable LP3 watermarks on all SNB machinesVille Syrjälä2019-05-161-1/+40
* drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changingImre Deak2018-04-261-3/+3
* drm/i915: Move init_clock_gating() back to where it wasVille Syrjälä2018-01-171-26/+18
* drm/i915: Do not rely on wm preservation for ILK watermarksMaarten Lankhorst2017-10-301-30/+21
* drm/i915: Use a mask when applying WaProgramL3SqcReg1DefaultOscar Mateo2017-10-181-3/+6
* drm/i915/gen10: implement gen 10 watermarks calculationsPaulo Zanoni2017-08-161-4/+13
* drm/i915/gen10: fix WM latency printingPaulo Zanoni2017-08-101-1/+1
* drm/i915/gen10: fix the gen 10 SAGV block timePaulo Zanoni2017-08-101-7/+6
* drm/i915/cnl: Enable SAGV for Cannonlake.Rodrigo Vivi2017-08-101-1/+2
* drm/i915/gen10+: use the SKL code for reading WM latenciesPaulo Zanoni2017-08-101-2/+4
* drm/i915: Add render decompression supportVille Syrjälä2017-08-101-2/+27
* drm/i915: enable WaDisableDopClkGating for sklPraveen Paneri2017-08-031-0/+6
* drm/i915: Include mbox details for pcode read/write failuresChris Wilson2017-07-281-8/+13
* drm/i915: Fix bad comparison in skl_compute_plane_wm, v2.Maarten Lankhorst2017-07-191-2/+2
* drm/i915/skl+: unify cpp value in WM calculationKumar, Mahesh2017-07-131-4/+2
* drm/i915/skl+: WM calculation don't require heightKumar, Mahesh2017-07-131-3/+1
* drm/i915: cleanup fixed-point wrappers namingKumar, Mahesh2017-07-131-32/+31
* drm/i915: Always perform internal fixed16 division in 64 bitsKumar, Mahesh2017-07-131-2/+2
* drm/i915/cnl: Inherit RPS stuff from previous platforms.Rodrigo Vivi2017-07-071-9/+9
* drm/i915: Avoid keeping waitboost active for signaling threadsChris Wilson2017-06-281-35/+22
* Revert "drm/i915/skl: New ddb allocation algorithm"Rodrigo Vivi2017-06-151-159/+98
* drm/i915/cfl: Introduce Display workarounds for Coffee Lake.Rodrigo Vivi2017-06-081-10/+11
* drm/i915: Fix SKL+ watermarks for 90/270 rotationVille Syrjälä2017-06-061-12/+24
* drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rateMaarten Lankhorst2017-06-011-4/+8
* drm/i915/skl+: consider max supported plane pixel rate while scalingMahesh Kumar2017-06-011-0/+87
* drm/i915/skl: New ddb allocation algorithmKumar, Mahesh2017-06-011-98/+159
* drm/i915: Always recompute watermarks when distrust_bios_wm is set, v2.Maarten Lankhorst2017-06-011-0/+9
* drm/i915/skl+: use linetime latency if ddb size is not availableKumar, Mahesh2017-05-171-9/+33
* drm/i915/skl+: Perform wm level calculations in separate functionKumar, Mahesh2017-05-171-24/+24
* drm/i915/skl+: Watermark calculation cleanupKumar, Mahesh2017-05-171-34/+19
* drm/i915/skl+: Fail the flip if ddb min requirement exceeds pipe allocationKumar, Mahesh2017-05-171-2/+11
* drm/i915/skl+: no need to memset againKumar, Mahesh2017-05-171-3/+1
* drm/i915/skl: Fail the flip if no FB for WM calculationKumar, Mahesh2017-05-171-1/+2
* drm/i915/skl+: calculate pixel_rate & relative_data_rate in fixed pointKumar, Mahesh2017-05-171-19/+19
* drm/i915: Use fixed_16_16 wrapper for division operationKumar, Mahesh2017-05-171-2/+2
* drm/i915: fix naming of fixed_16_16 wrapper.Kumar, Mahesh2017-05-171-3/+3
* drm/i915: Add g4x watermark tracepointVille Syrjälä2017-05-101-0/+5
* drm/i915: Enable HPLL watermarks on g4xVille Syrjälä2017-05-101-1/+2
* drm/i915: Two stage watermarks for g4xVille Syrjälä2017-05-101-216/+724
* drm/i915: Apply the g4x TLB miss w/a to SR watermarks as wellVille Syrjälä2017-05-101-6/+9
* drm/i915: Refactor wm calculationsVille Syrjälä2017-05-101-72/+149
* drm/i915: Refactor the g4x TLB miss w/a to a helperVille Syrjälä2017-05-101-7/+20
* drm/i915: Fix the g4x watermark TLB miss workaroundVille Syrjälä2017-05-101-5/+6
* drm/i915: Fix cursor 'cpp' in watermark calculatins for old platformsVille Syrjälä2017-05-101-5/+5
* drm/i915: Document CxSRVille Syrjälä2017-05-101-0/+37
* drm/i915: Make vlv/chv watermark debug print less crypticVille Syrjälä2017-05-101-1/+1
* drm/i915: Rename bunch of vlv_ watermark structures to g4x_Ville Syrjälä2017-05-101-7/+7
* drm/i915: s/vlv_num_wm_levels/intel_wm_num_levels/Ville Syrjälä2017-05-101-9/+9
* drm/i915: Drop the debug message from vlv_get_fifo_size()Ville Syrjälä2017-05-101-7/+0