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path: root/drivers/gpu/drm/i915/intel_pm.c
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* BackMerge tag 'v5.15-rc7' into drm-nextDave Airlie2021-10-281-0/+12
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| * drm/i915: Extend the async flip VT-d w/a to skl/bxtVille Syrjälä2021-10-051-0/+12
* | drm/i915: split out intel_pcode.[ch] to separate fileJani Nikula2021-10-141-1/+1
* | drm/i915: split out vlv sideband to a separate fileJani Nikula2021-10-141-0/+1
* | drm/i195: Make the async flip VT-d workaround dynamicVille Syrjälä2021-10-041-26/+0
* | drm/i915: Extend the async flip VT-d w/a to skl/bxtVille Syrjälä2021-10-041-0/+12
* | drm/i915: constify display wm vtableDave Airlie2021-09-291-23/+57
* | drm/i915: constify clock gating init vtable.Dave Airlie2021-09-291-24/+54
* | drm/i915: split watermark vfuncs from display vtable.Dave Airlie2021-09-291-20/+20
* | drm/i915: split clock gating init from display vtableDave Airlie2021-09-291-24/+24
* | drm/i915/wm: provide wrappers around watermark vfuncs calls (v3)Dave Airlie2021-09-291-39/+0
* | drm/i915: make update_wm take a dev_priv.Dave Airlie2021-09-291-13/+7
* | drm/i915/pm: drop get_fifo_size vfunc.Dave Airlie2021-09-291-9/+11
* | drm/i915: Fix HPLL watermark readout for g4xVille Syrjälä2021-09-231-2/+5
* | drm/i915: Apply WaUse32BppForSRWM to elk as well as ctgVille Syrjälä2021-09-221-8/+4
* | drm/i915: Fix g4x cxsr enable conditionVille Syrjälä2021-09-221-3/+2
* | drm/i915: Use u8 consistently for active_planes bitmaskVille Syrjälä2021-09-221-3/+3
* | drm/i915/dg2: Memory latency values from pcode must be doubledMatt Roper2021-08-251-14/+15
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* Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/...Dave Airlie2021-08-121-42/+121
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| * drm/i915: remove explicit CNL handling from intel_pm.cLucas De Marchi2021-07-301-40/+1
| * drm/i915/dg2: Add dbuf programmingMatt Roper2021-07-221-1/+119
| * drm/i915: Make display workaround upper bounds exclusiveMatt Roper2021-07-211-1/+1
| * Merge branch 'topic/revid_steppings' into drm-intel-nextMatt Roper2021-07-141-1/+1
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* | \ Merge tag 'drm-intel-gt-next-2021-08-06-1' of ssh://git.freedesktop.org/git/d...Dave Airlie2021-08-121-14/+8
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| * | drm/i915: Make GT workaround upper bounds exclusiveMatt Roper2021-07-211-3/+3
| * | drm/i915: Program DFR enable/disable as a GT workaroundMatt Roper2021-07-211-8/+0
| * | Merge branch 'topic/revid_steppings' into drm-intel-gt-nextMatt Roper2021-07-141-1/+1
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| | * drm/i915/dg1: Use revid->stepping tablesMatt Roper2021-07-141-1/+1
| * | drm/i915: Settle on "adl-x" in WA commentsJosé Roberto de Souza2021-07-131-2/+2
| * | drm/i915/adl_p: Add initial ADL_P WorkaroundsClint Taylor2021-06-151-3/+5
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* | drm/i915/display: use max_level to control loopLucas De Marchi2021-06-251-5/+4
* | drm/i915/display: fix level 0 adjustement on display ver >= 12Lucas De Marchi2021-06-251-6/+7
* | drm/i915: Clean up pre-skl wm calling conventionVille Syrjälä2021-06-241-47/+52
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* drm/i915/adl_p: Same slices mask is not same Dbuf stateStanislav Lisovskiy2021-06-091-2/+4
* drm/i915: replace IS_GEN and friends with GRAPHICS_VERLucas De Marchi2021-06-071-7/+7
* drm/i915: Initialize the mbus_offset to fix Klockwork issueManasi Navare2021-06-041-1/+1
* drm/i915/adl_p: MBUS programmingVandita Kulkarni2021-05-191-8/+84
* drm/i915: Introduce MBUS relative dbuf offsetsVille Syrjälä2021-05-191-6/+34
* drm/i915/adl_p: Add ddb allocation supportVandita Kulkarni2021-05-191-1/+120
* drm/i915/adl_p: Add dedicated SAGV watermarksMatt Roper2021-05-191-4/+50
* Merge drm/drm-next into drm-intel-nextRodrigo Vivi2021-05-171-1/+1
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| * Merge tag 'drm-next-2021-04-28' of git://anongit.freedesktop.org/drm/drmLinus Torvalds2021-04-281-240/+302
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| * | Fix misc new gcc warningsLinus Torvalds2021-04-271-1/+1
| * | drm/i915: Don't zero out the Y plane's watermarksVille Syrjälä2021-04-121-2/+2
| * | drm/i915: Workaround async flip + VT-d corruption on HSW/BDWVille Syrjälä2021-03-171-1/+15
* | | drm/i915/adl_p: Implement Wa_22011091694José Roberto de Souza2021-05-141-1/+11
* | | drm/i915/xelpd: Increase maximum watermark lines to 255Matt Roper2021-05-141-4/+11
* | | drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä2021-05-051-0/+1
* | | drm/i915: Polish for_each_dbuf_slice()Ville Syrjälä2021-04-211-22/+12
* | | drm/i915: Use intel_dbuf_slice_size()Ville Syrjälä2021-04-211-6/+3
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