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* Merge tag 'drm-msm-fixes-2024-08-19' of ↵Dave Airlie3 days8-30/+37
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.freedesktop.org/drm/msm into drm-fixes Fixes for v6.11-rc5 1) Fixes from the virtual plane series, namely - fix the list of formats for QCM2290 since it has no YUV support - minor fix in dpu_plane_atomic_check_pipe() to check only for csc and not csc and scaler while allowing yuv formats - take rotation into account while allocating virtual planes 2) Fix to cleanup FB if dpu_format_populate_layout() fails. This fixes the warning splat during DRM file closure 3) Fix to reset the phy link params before re-starting link training. This fixes the 100% link training failure when someone starts modetest while cable is connected 4) Long pending fix to fix a visual corruption seen for 4k modes. Root-cause was we cannot support 4k@30 with 30bpp with 2 lanes so this is a critical fix to use 24bpp for such cases 5) Fix to move dpu encoder's connector assignment to atomic_enable(). This fixes the NULL ptr crash for cases when there is an atomic_enable() without atomic_modeset() after atomic_disable() . This happens for connectors_changed case of crtc. It fixes a NULL ptr crash reported during hotplug. 6) Fix to simplify DPU's debug macros without which dynamic debug does not work as expected 7) Fix the highest bank bit setting for sc7180 8) adreno: fix error return if missing firmware-name Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvxF2p3-AsjUydmSYrA0Vb+Ea7nh3VtNX0pT0Ae_Me-Kw@mail.gmail.com
| * drm/msm/adreno: Fix error return if missing firmware-nameRob Clark10 days1-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | -ENODEV is used to signify that there is no zap shader for the platform, and the CPU can directly take the GPU out of secure mode. We want to use this return code when there is no zap-shader node. But not when there is, but without a firmware-name property. This case we want to treat as-if the needed fw is not found. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/604564/
| * drm/msm: fix the highest_bank_bit for sc7180Abhinav Kumar12 days1-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sc7180 programs the ubwc settings as 0x1e as that would mean a highest bank bit of 14 which matches what the GPU sets as well. However, the highest_bank_bit field of the msm_mdss_data which is being used to program the SSPP's fetch configuration is programmed to a highest bank bit of 16 as 0x3 translates to 16 and not 14. Fix the highest bank bit field used for the SSPP to match the mdss and gpu settings. Fixes: 6f410b246209 ("drm/msm/mdss: populate missing data") Reviewed-by: Rob Clark <robdclark@gmail.com> Tested-by: Stephen Boyd <swboyd@chromium.org> # Trogdor.Lazor Patchwork: https://patchwork.freedesktop.org/patch/607625/ Link: https://lore.kernel.org/r/20240808235227.2701479-1-quic_abhinavk@quicinc.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
| * drm/msm/dpu: take plane rotation into account for wide planesDmitry Baryshkov2024-08-051-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Take into account the plane rotation and flipping when calculating src positions for the wide plane parts. This is not an issue yet, because rotation is only supported for the UBWC planes and wide UBWC planes are rejected anyway because in parallel multirect case only the half of the usual width is supported for tiled formats. However it's better to fix this now rather than stumbling upon it later. Fixes: 80e8ae3b38ab ("drm/msm/dpu: add support for wide planes") Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601059/ Link: https://lore.kernel.org/r/20240627-dpu-virtual-wide-v5-3-5efb90cbb8be@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
| * drm/msm/dpu: relax YUV requirementsDmitry Baryshkov2024-08-051-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | YUV formats require only CSC to be enabled. Even decimated formats should not require scaler. Relax the requirement and don't check for the scaler block while checking if YUV format can be enabled. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/601049/ Link: https://lore.kernel.org/r/20240627-dpu-virtual-wide-v5-2-5efb90cbb8be@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
| * drm/msm/dpu: limit QCM2290 to RGB formats onlyDmitry Baryshkov2024-08-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The QCM2290 doesn't have CSC blocks, so it can not support YUV formats even on ViG blocks. Fix the formats declared by _VIG_SBLK_NOSCALE(). Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/601048/ Link: https://lore.kernel.org/r/20240627-dpu-virtual-wide-v5-1-5efb90cbb8be@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
| * drm/msm/dpu: cleanup FB if dpu_format_populate_layout failsDmitry Baryshkov2024-08-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the dpu_format_populate_layout() fails, then FB is prepared, but not cleaned up. This ends up leaking the pin_count on the GEM object and causes a splat during DRM file closure: msm_obj->pin_count WARNING: CPU: 2 PID: 569 at drivers/gpu/drm/msm/msm_gem.c:121 update_lru_locked+0xc4/0xcc [...] Call trace: update_lru_locked+0xc4/0xcc put_pages+0xac/0x100 msm_gem_free_object+0x138/0x180 drm_gem_object_free+0x1c/0x30 drm_gem_object_handle_put_unlocked+0x108/0x10c drm_gem_object_release_handle+0x58/0x70 idr_for_each+0x68/0xec drm_gem_release+0x28/0x40 drm_file_free+0x174/0x234 drm_release+0xb0/0x160 __fput+0xc0/0x2c8 __fput_sync+0x50/0x5c __arm64_sys_close+0x38/0x7c invoke_syscall+0x48/0x118 el0_svc_common.constprop.0+0x40/0xe0 do_el0_svc+0x1c/0x28 el0_svc+0x4c/0x120 el0t_64_sync_handler+0x100/0x12c el0t_64_sync+0x190/0x194 irq event stamp: 129818 hardirqs last enabled at (129817): [<ffffa5f6d953fcc0>] console_unlock+0x118/0x124 hardirqs last disabled at (129818): [<ffffa5f6da7dcf04>] el1_dbg+0x24/0x8c softirqs last enabled at (129808): [<ffffa5f6d94afc18>] handle_softirqs+0x4c8/0x4e8 softirqs last disabled at (129785): [<ffffa5f6d94105e4>] __do_softirq+0x14/0x20 Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/600714/ Link: https://lore.kernel.org/r/20240625-dpu-mode-config-width-v5-1-501d984d634f@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
| * drm/msm/dp: reset the link phy params before link trainingAbhinav Kumar2024-08-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before re-starting link training reset the link phy params namely the pre-emphasis and voltage swing levels otherwise the next link training begins at the previously cached levels which can result in link training failures. Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8350-HDK Reviewed-by: Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/605946/ Link: https://lore.kernel.org/r/20240725220450.131245-1-quic_abhinavk@quicinc.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
| * drm/msm/dpu: move dpu_encoder's connector assignment to atomic_enable()Abhinav Kumar2024-08-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For cases where the crtc's connectors_changed was set without enable/active getting toggled , there is an atomic_enable() call followed by an atomic_disable() but without an atomic_mode_set(). This results in a NULL ptr access for the dpu_encoder_get_drm_fmt() call in the atomic_enable() as the dpu_encoder's connector was cleared in the atomic_disable() but not re-assigned as there was no atomic_mode_set() call. Fix the NULL ptr access by moving the assignment for atomic_enable() and also use drm_atomic_get_new_connector_for_encoder() to get the connector from the atomic_state. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/59 Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8350-HDK Patchwork: https://patchwork.freedesktop.org/patch/606729/ Link: https://lore.kernel.org/r/20240731191723.3050932-1-quic_abhinavk@quicinc.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
| * drm/msm/dp: fix the max supported bpp logicAbhinav Kumar2024-08-051-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the dp_panel_get_supported_bpp() API to return the minimum supported bpp correctly for relevant cases and use this API to correct the behavior of DP driver which hard-codes the max supported bpp to 30. This is incorrect because the number of lanes and max data rate supported by the lanes need to be taken into account. Replace the hardcoded limit with the appropriate math which accounts for the accurate number of lanes and max data rate. changes in v2: - Fix the dp_panel_get_supported_bpp() and use it - Drop the max_t usage as dp_panel_get_supported_bpp() already returns the min_bpp correctly now changes in v3: - replace min_t with just min as all params are u32 Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support") Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/43 Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8350-HDK Reviewed-by: Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/607073/ Link: https://lore.kernel.org/r/20240805202009.1120981-1-quic_abhinavk@quicinc.com Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
| * drm/msm/dpu: don't play tricks with debug macrosDmitry Baryshkov2024-08-051-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DPU debugging macros need to be converted to a proper drm_debug_* macros, however this is a going an intrusive patch, not suitable for a fix. Wire DPU_DEBUG and DPU_DEBUG_DRIVER to always use DRM_DEBUG_DRIVER to make sure that DPU debugging messages always end up in the drm debug messages and are controlled via the usual drm.debug mask. I don't think that it is a good idea for a generic DPU_DEBUG macro to be tied to DRM_UT_KMS. It is used to report a debug message from driver, so by default it should go to the DRM_UT_DRIVER channel. While refactoring debug macros later on we might end up with particular messages going to ATOMIC or KMS, but DRIVER should be the default. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/606932/ Link: https://lore.kernel.org/r/20240802-dpu-fix-wb-v2-2-7eac9eb8e895@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
* | Merge tag 'iommu-updates-v6.11' of ↵Linus Torvalds2024-07-191-2/+5
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux Pull iommu updates from Will Deacon: "Core: - Support for the "ats-supported" device-tree property - Removal of the 'ops' field from 'struct iommu_fwspec' - Introduction of iommu_paging_domain_alloc() and partial conversion of existing users - Introduce 'struct iommu_attach_handle' and provide corresponding IOMMU interfaces which will be used by the IOMMUFD subsystem - Remove stale documentation - Add missing MODULE_DESCRIPTION() macro - Misc cleanups Allwinner Sun50i: - Ensure bypass mode is disabled on H616 SoCs - Ensure page-tables are allocated below 4GiB for the 32-bit page-table walker - Add new device-tree compatible strings AMD Vi: - Use try_cmpxchg64() instead of cmpxchg64() when updating pte Arm SMMUv2: - Print much more useful information on context faults - Fix Qualcomm TBU probing when CONFIG_ARM_SMMU_QCOM_DEBUG=n - Add new Qualcomm device-tree bindings Arm SMMUv3: - Support for hardware update of access/dirty bits and reporting via IOMMUFD - More driver rework from Jason, this time updating the PASID/SVA support to prepare for full IOMMUFD support - Add missing MODULE_DESCRIPTION() macro - Minor fixes and cleanups NVIDIA Tegra: - Fix for benign fwspec initialisation issue exposed by rework on the core branch Intel VT-d: - Use try_cmpxchg64() instead of cmpxchg64() when updating pte - Use READ_ONCE() to read volatile descriptor status - Remove support for handling Execute-Requested requests - Avoid calling iommu_domain_alloc() - Minor fixes and refactoring Qualcomm MSM: - Updates to the device-tree bindings" * tag 'iommu-updates-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (72 commits) iommu/tegra-smmu: Pass correct fwnode to iommu_fwspec_init() iommu/vt-d: Fix identity map bounds in si_domain_init() iommu: Move IOMMU_DIRTY_NO_CLEAR define dt-bindings: iommu: Convert msm,iommu-v0 to yaml iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address() iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH docs: iommu: Remove outdated Documentation/userspace-api/iommu.rst arm64: dts: fvp: Enable PCIe ATS for Base RevC FVP iommu/of: Support ats-supported device-tree property dt-bindings: PCI: generic: Add ats-supported property iommu: Remove iommu_fwspec ops OF: Simplify of_iommu_configure() ACPI: Retire acpi_iommu_fwspec_ops() iommu: Resolve fwspec ops automatically iommu/mediatek-v1: Clean up redundant fwspec checks RDMA/usnic: Use iommu_paging_domain_alloc() wifi: ath11k: Use iommu_paging_domain_alloc() wifi: ath10k: Use iommu_paging_domain_alloc() drm/msm: Use iommu_paging_domain_alloc() vhost-vdpa: Use iommu_paging_domain_alloc() ...
| * drm/msm: Use iommu_paging_domain_alloc()Lu Baolu2024-07-041-2/+5
| | | | | | | | | | | | | | | | | | | | The domain allocated in msm_iommu_new() is for the @dev. Replace iommu_domain_alloc() with iommu_paging_domain_alloc() to make it explicit. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240610085555.88197-6-baolu.lu@linux.intel.com Signed-off-by: Will Deacon <will@kernel.org>
| * drm/msm: remove python 3.9 dependency for compiling msmAbhinav Kumar2024-05-301-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 5acf49119630 ("drm/msm: import gen_header.py script from Mesa"), compilation is broken on machines having python versions older than 3.9 due to dependency on argparse.BooleanOptionalAction. Switch to use simple bool for the validate flag to remove the dependency. Fixes: 5acf49119630 ("drm/msm: import gen_header.py script from Mesa") Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240507230440.3384949-1-quic_abhinavk@quicinc.com
* | drm/msm/gem: Add missing rcu_dereference()Rob Clark2024-07-021-1/+1
| | | | | | | | | | | | | | | | | | Fixes a sparse "different address spaces" error. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406280050.syeEwLTE-lkp@intel.com/ Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/601612/
* | drm/msm/a6xx: Add missing __always_unusedRob Clark2024-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | The __build_asserts() function only exists to have a place to put build-time asserts. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202407010401.rfunrBSx-lkp@intel.com/ Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601606/
* | drm/msm/adreno: Add support for Adreno 505 GPUDaniil Titov2024-07-013-12/+35
| | | | | | | | | | | | | | | | | | | | | | This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz), SDM439 (650 MHz). Signed-off-by: Daniil Titov <daniilt971@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Barnabás Czémán <trabarni@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/601411/ Signed-off-by: Rob Clark <robdclark@chromium.org>
* | drm/msm/dpu: check ubwc support before adding compressed formatsAbhinav Kumar2024-07-011-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On QCM2290 chipset DPU does not support UBWC. Add a dpu cap to indicate this and do not expose compressed formats in this case. changes since RFC: - use ubwc enc and dec version of mdss_data instead of catalog to decide if ubwc is supported Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601392/ Signed-off-by: Rob Clark <robdclark@chromium.org>
* | drm/msm/adreno: Introduce gmu_chipid for a740 & a750Akhil P Oommen2024-06-292-22/+3
| | | | | | | | | | | | | | | | | | To simplify, introduce the new gmu_chipid for a740 & a750 GPUs. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601396/ Signed-off-by: Rob Clark <robdclark@chromium.org>
* | drm/msm/adreno: Add support for X185 GPUAkhil P Oommen2024-06-295-3/+36
| | | | | | | | | | | | | | | | | | | | Add support in drm/msm driver for the Adreno X185 gpu found in Snapdragon X1 Elite chipset. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601399/ Signed-off-by: Rob Clark <robdclark@chromium.org>
* | drm/msm/adreno: fix a743 and a740 cx mem initNeil Armstrong2024-06-291-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable the call to qcom_scm_gpu_init_regs() for a730 and a740 after init failures on the HDK8550 and HDK8450 platforms: msm_dpu ae01000.display-controller: failed to load adreno gpu msm_dpu ae01000.display-controller: failed to bind 3d00000.gpu (ops a3xx_ops [msm]): -5 msm_dpu ae01000.display-controller: adev bind failed: -5 While debugging, it happens the call to: qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ) returns -5 and makes the gpu fail to initialize. Remove the scm call since it's not done downstream either and works fine without. Fixes: 14b27d5df3ea ("drm/msm/a7xx: Initialize a750 "software fuse"") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/600972/ Signed-off-by: Rob Clark <robdclark@chromium.org>
* | drm/msm/adreno: fix a7xx gpu initNeil Armstrong2024-06-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpulist has twice the a6xx gpulist, replace the second one with the a7xx gpulist. Solves: msm_dpu ae01000.display-controller: Unknown GPU revision: 7.3.0.1 msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.10.1 msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.20.1 on SM8450, SM8550 & SM8560. Fixes: 8ed322f632a9 ("drm/msm/adreno: Split up giant device table") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/600939/ Signed-off-by: Rob Clark <robdclark@chromium.org>
* | Revert "drm/msm/a6xx: Poll for GBIF unhalt status in hw_init"Konrad Dybcio2024-06-291-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f6ebff4fe810 ("drm/msm/adreno: De-spaghettify the use of memory barriers") made some fixups relating to write arrival, ensuring that the GPU's memory interface has *really really really* been told to come out of reset. That in turn rendered the hacky commit being reverted no longer necessary. Get rid of it. This reverts commit b77532803d11 ("drm/msm/a6xx: Poll for GBIF unhalt status in hw_init") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/600870/ Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
* | drm/msm/adreno: De-spaghettify the use of memory barriersKonrad Dybcio2024-06-292-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory barriers help ensure instruction ordering, NOT time and order of actual write arrival at other observers (e.g. memory-mapped IP). On architectures employing weak memory ordering, the latter can be a giant pain point, and it has been as part of this driver. Moreover, the gpu_/gmu_ accessors already use non-relaxed versions of readl/writel, which include r/w (respectively) barriers. Replace the barriers with a readback (or drop altogether where possible) that ensures the previous writes have exited the write buffer (as the CPU must flush the write to the register it's trying to read back). Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/600869/ Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
* | drm/msm/dpu: remove CRTC frame event callback registrationDmitry Baryshkov2024-06-255-64/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | The frame event callback is always set to dpu_crtc_frame_event_cb() (or to NULL) and the data is always either the CRTC itself or NULL (correpondingly). Thus drop the event callback registration, call the dpu_crtc_frame_event_cb() directly and gate on the dpu_enc->crtc assigned using dpu_encoder_assign_crtc(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/600751/ Link: https://lore.kernel.org/r/20240625-dpu-no-crtc-register-v3-1-1b161df13776@linaro.org
* | drm/msm/dsi: Add phy configuration for MSM8937Daniil Titov2024-06-253-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only difference from existing msm8916 configuration is number of phy and io_start addresses. Signed-off-by: Daniil Titov <daniilt971@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Barnabás Czémán <trabarni@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/600518/ Link: https://lore.kernel.org/r/20240623-dsi-v2-4-a0ca70fb4846@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/mdp5: Add MDP5 configuration for MSM8937Daniil Titov2024-06-251-0/+88
| | | | | | | | | | | | | | | | | | | | | | Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937. Signed-off-by: Daniil Titov <daniilt971@gmail.com> Signed-off-by: Barnabás Czémán <trabarni@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/600513/ Link: https://lore.kernel.org/r/20240623-dsi-v2-2-a0ca70fb4846@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/mdp5: Remove MDP_CAP_SRC_SPLIT from msm8x53_configBarnabás Czémán2024-06-251-2/+1
| | | | | | | | | | | | | | | | | | | | | | Remove MDP_CAP_SRC_SPLIT from msm8x53_config because it is not referenced in downstream. Fixes: fb25d4474fa0 ("drm/msm/mdp5: Add configuration for MDP v1.16") Signed-off-by: Barnabás Czémán <trabarni@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/600521/ Link: https://lore.kernel.org/r/20240624-msm8953-mdp-fix-v1-1-be4d3262ebe3@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dp: switch to struct drm_edidJani Nikula2024-06-243-40/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prefer the struct drm_edid based functions for reading the EDID and updating the connector. Simplify the flow by updating the EDID property when the EDID is read instead of at .get_modes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/593976/ Link: https://lore.kernel.org/r/93d6c446ed4831dadfb4a77635a67cf5f27e19ff.1715691257.git.jani.nikula@intel.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dpu: guard ctl irq callback register/unregisterBarnabás Czémán2024-06-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts, so better to skip CTL irq callback register/unregister make dpu_ctl_cfg be able to define without intr_start. Signed-off-by: Barnabás Czémán <trabarni@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/596854/ Link: https://lore.kernel.org/r/20240509-ctl_irq-v1-1-9433f2da9dc7@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dpu: rename dpu_hw_setup_vsync_source functionsDmitry Baryshkov2024-06-241-7/+7
| | | | | | | | | | | | | | | | | | | | | | Rename dpu_hw_setup_vsync_source functions to make the names match the implementation: on DPU 5.x the TOP only contains timer setup, while 3.x and 4.x used MDP_VSYNC_SEL register to select TE source. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/598745/ Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-8-67a0116b5366@linaro.org
* | drm/msm/dpu: support setting the TE sourceDmitry Baryshkov2024-06-241-1/+43
| | | | | | | | | | | | | | | | | | | | Make the DPU driver use the TE source specified in the DT. If none is specified, the driver defaults to the first GPIO (mdp_vsync_p). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/598733/ Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-7-67a0116b5366@linaro.org
* | drm/msm/dsi: parse vsync source from device treeDmitry Baryshkov2024-06-244-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Allow board's device tree to specify the vsync source (aka TE source). If the property is omitted, the display controller driver will use the default setting. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> [DB: fixed clearing of return value if there is no TE property] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/598740/ Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-6-67a0116b5366@linaro.org
* | drm/msm/dpu: rework vsync_source handlingDmitry Baryshkov2024-06-243-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | The struct msm_display_info has is_te_using_watchdog_timer field which is neither set anywhere nor is flexible enough to specify different sources. Replace it with the field specifying the vsync source using enum dpu_vsync_source. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/598738/ Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-5-67a0116b5366@linaro.org
* | drm/msm/dpu: pull the is_cmd_mode out of _dpu_encoder_update_vsync_source()Dmitry Baryshkov2024-06-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Setting vsync source makes sense only for DSI CMD panels. Pull the is_cmd_mode condition out of the function into the calling code, so that it becomes more explicit. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/598736/ Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-4-67a0116b5366@linaro.org
* | drm/msm/dsi: drop unused GPIOs handlingDmitry Baryshkov2024-06-241-37/+0
| | | | | | | | | | | | | | | | | | | | | | | | Neither disp-enable-gpios nor disp-te-gpios are defined in the schema. None of the board DT files use those GPIO pins. Drop them from the driver. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/598734/ Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-3-67a0116b5366@linaro.org
* | drm/msm/dpu: convert vsync source defines to the enumDmitry Baryshkov2024-06-245-16/+18
| | | | | | | | | | | | | | | | | | | | Add enum dpu_vsync_source instead of a series of defines. Use this enum to pass vsync information. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/598743/ Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-2-67a0116b5366@linaro.org
* | drm/msm/dpu: drop validity checks for clear_pending_flush() ctl opAbhinav Kumar2024-06-233-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clear_pending_flush() ctl op is always assigned irrespective of the DPU hardware revision. Hence there is no needed to check whether the op has been assigned before calling it. Drop the checks across the driver for clear_pending_flush() and also update its documentation that it is always expected to be assigned. changes in v2: - instead of adding more validity checks just drop the one for clear_pending_flush - update the documentation for clear_pending_flush() ctl op - update the commit text reflecting these changes changes in v3: - simplify the documentation of clear_pending_flush Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/464fbd84-0d1c-43c3-a40b-31656ac06456@moroto.mountain/T/ Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/600241/ Link: https://lore.kernel.org/r/20240620201731.3694593-1-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm: mdss: Add SM7150 supportDanila Tikhonov2024-06-231-0/+8
| | | | | | | | | | | | | | | | | | | | Add support for MDSS on SM7150. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/599133/ Link: https://lore.kernel.org/r/20240614215855.82093-5-danila@jiaxyga.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dpu: Add SM7150 supportDanila Tikhonov2024-06-234-0/+338
| | | | | | | | | | | | | | | | | | | | | | Add definitions for the display hardware used on the Qualcomm SM7150 platform. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/599129/ Link: https://lore.kernel.org/r/20240614215855.82093-3-danila@jiaxyga.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dsi: add a comment to explain pkt_per_line encodingJonathan Marek2024-06-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Jun Nie <jun.nie@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/596236/ Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-6-2ab1d334c657@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WCJonathan Marek2024-06-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Video mode DSC won't work if this field is not set correctly. Set it to fix video mode DSC (for slice_per_pkt==1 cases at least). Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Jun Nie <jun.nie@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/596234/ Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-5-2ab1d334c657@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dsi: set video mode widebus enable bit when widebus is enabledJonathan Marek2024-06-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value returned by msm_dsi_wide_bus_enabled() doesn't match what the driver is doing in video mode. Fix that by actually enabling widebus for video mode. Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Jun Nie <jun.nie@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Patchwork: https://patchwork.freedesktop.org/patch/596232/ Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-4-2ab1d334c657@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dpu: enable compression bit in cfg2 for DSCJun Nie2024-06-233-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable compression bit in cfg2 register for DSC in the DSI case per hardware version. Signed-off-by: Jun Nie <jun.nie@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/596231/ Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-3-2ab1d334c657@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dpu: adjust data width for widen bus caseJun Nie2024-06-231-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | data is valid for only half the active window if widebus is enabled Signed-off-by: Jun Nie <jun.nie@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/596229/ Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-2-2ab1d334c657@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dpu: fix video mode DSC for DSIJonathan Marek2024-06-233-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add width change in DPU timing for DSC compression case to work with DSI video mode. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Jun Nie <jun.nie@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/596227/ Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-1-2ab1d334c657@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dsi: Remove dsi_phy_write_[un]delay()Konrad Dybcio2024-06-233-33/+54
| | | | | | | | | | | | | | | | | | | | | | These are dummy wrappers that do literally nothing interesting. Remove them. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/590703/ Link: https://lore.kernel.org/r/20240423-topic-msm_cleanup-v1-2-b30f39f43b90@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/dsi: Remove dsi_phy_read/write()Konrad Dybcio2024-06-237-703/+645
| | | | | | | | | | | | | | | | | | | | | | These are dummy wrappers that do literally nothing interesting. Remove them. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/590700/ Link: https://lore.kernel.org/r/20240423-topic-msm_cleanup-v1-1-b30f39f43b90@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
* | drm/msm/a7xx: Add missing register writes from downstreamConnor Abbott2024-06-211-0/+11
| | | | | | | | | | | | | | | | | | This isn't known to fix anything yet, but it's a good idea to add it. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/592043/ Signed-off-by: Rob Clark <robdclark@chromium.org>
* | drm/msm: Add MSM_PARAM_RAYTRACING uapiConnor Abbott2024-06-211-0/+3
| | | | | | | | | | | | | | | | | | | | Expose the value of the software fuse to userspace. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/592044/ Signed-off-by: Rob Clark <robdclark@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-25 22:53:14 +0000