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path: root/drivers/gpu
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* drm/i915/dsb: Use non-posted register writes for legacy LUTVille Syrjälä2023-09-271-0/+11
* drm/i915/dsb: Load LUTs using the DSB during vblankVille Syrjälä2023-09-274-7/+32
* drm/i915/dsb: Don't use DSB to load the LUTs during full modesetVille Syrjälä2023-09-271-0/+4
* drm/i915/dsb: Add support for non-posted DSB registers writesVille Syrjälä2023-09-272-0/+23
* drm/i915/dsb: Introduce intel_dsb_reg_write_masked()Ville Syrjälä2023-09-272-0/+20
* drm/i915/dsb: Introduce intel_dsb_noop()Ville Syrjälä2023-09-272-0/+10
* drm/i915/dsb: Define the contents of some intstructions bit betterVille Syrjälä2023-09-271-4/+8
* drm/i915/dsb: Define more DSB bitsVille Syrjälä2023-09-271-0/+31
* drm/i915/dsb: Use non-locked register accessVille Syrjälä2023-09-271-9/+9
* drm/i915/cx0: prefer forward declarations over includesJani Nikula2023-09-261-6/+8
* drm/i915/dp: refactor aux_ch_name()Jani Nikula2023-09-262-18/+25
* drm/i915/irq: Clear GFX_MSTR_IRQ as part of IRQ resetGustavo Sousa2023-09-251-0/+2
* drm/i915: Zap some empty linesTvrtko Ursulin2023-09-251-7/+0
* drm/i915/display: Print display info inside driver display initializationBalasubramani Vivekanandan2023-09-222-2/+5
* drm/i915/bios: Fixup h/vsync_end instead of h/vtotalVille Syrjälä2023-09-211-8/+15
* drm/i915/lnl: Start using CDCLK through PLLStanislav Lisovskiy2023-09-212-2/+8
* drm/i915/xe2lpd: Add DC state supportMatt Roper2023-09-212-1/+21
* drm/i915/xe2lpd: Add display power wellRavi Kumar Vodapalli2023-09-214-1/+82
* drm/i915/lnl: Add CDCLK tableStanislav Lisovskiy2023-09-211-1/+29
* drm/i915/lnl: Add gmbus/ddc supportLucas De Marchi2023-09-212-2/+6
* drm/i915/xe2lpd: Extend Wa_15010685871Lucas De Marchi2023-09-211-3/+4
* drm/i915/xe2lpd: Add support for HPDGustavo Sousa2023-09-211-2/+19
* drm/i915/xe2lpd: Enable odd size and panning for planar yuvJuha-Pekka Heikkilä2023-09-211-0/+8
* drm/i915/xe2lpd: Read pin assignment from IOMLuca Coelho2023-09-212-0/+29
* drm/i915/xe2lpd: Handle port AUX interruptsGustavo Sousa2023-09-213-4/+8
* drm/i915/xe2lpd: Re-order DP AUX regsLucas De Marchi2023-09-213-9/+24
* drm/i915/display: Use _PICK_EVEN_2RANGES() in DP AUX regsLucas De Marchi2023-09-211-20/+10
* drm/i915/display: Fix style and conventions for DP AUX regsLucas De Marchi2023-09-211-37/+35
* drm/i915/xe2lpd: Register DE_RRMR has been removedClint Taylor2023-09-211-1/+1
* drm/i915/xe2lpd: Don't try to program PLANE_AUX_DISTMatt Roper2023-09-211-1/+1
* drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocationStanislav Lisovskiy2023-09-212-10/+12
* drm/i915/xe2lpd: Add fake PCHGustavo Sousa2023-09-212-1/+6
* drm/i915: Re-order if/else ladder in intel_detect_pch()Lucas De Marchi2023-09-211-5/+8
* drm/i915/display: Remove FBC capability from fused off pipesClint Taylor2023-09-211-0/+3
* drm/i915/xe2lpd: FBC is now supported on all pipesMatt Roper2023-09-212-0/+6
* drm/i915/lnl: Add display definitionsBalasubramani Vivekanandan2023-09-211-0/+5
* drm/i915/xelpdp: Add XE_LPDP_FEATURESLucas De Marchi2023-09-211-11/+46
* Revert "drm/i915/mst: Populate connector->ddc"Ville Syrjälä2023-09-211-4/+2
* drm/i915: add a note about fec_enable with 128b/132bJani Nikula2023-09-211-1/+6
* drm/i915: Implement transcoder LRR for TGL+Ville Syrjälä2023-09-206-11/+70
* drm/i915: Assert that VRR is off during vblank evasion if necessaryVille Syrjälä2023-09-201-0/+4
* drm/i915: Update VRR parameters in fastsetVille Syrjälä2023-09-201-8/+26
* drm/i915: Disable VRR during seamless M/N changesVille Syrjälä2023-09-201-2/+4
* drm/i915: Validate that the timings are within the VRR rangeVille Syrjälä2023-09-201-2/+2
* drm/i915: Relocate is_in_vrr_range()Ville Syrjälä2023-09-203-13/+14
* drm/i915: Optimize out redundant M/N updatesVille Syrjälä2023-09-201-1/+3
* drm/i915: Adjust seamless_m_n flag behaviourVille Syrjälä2023-09-205-12/+17
* drm/i915: Enable VRR later during fastsetsVille Syrjälä2023-09-202-20/+36
* drm/i915: Extract intel_crtc_vblank_evade_scanlines()Ville Syrjälä2023-09-201-22/+31
* drm/i915: Change intel_pipe_update_{start,end}() calling conventionVille Syrjälä2023-09-203-10/+18