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path: root/drivers/irqchip/irq-sifive-plic.c
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* Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2022-08-061-3/+4
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| * riscv: cpu: Add 64bit hartid support on RV64Sunil V L2022-07-191-3/+4
* | irqchip/sifive-plic: Separate the enable and mask operationsSamuel Holland2022-07-101-21/+34
* | irqchip/sifive-plic: Make better use of the effective affinity maskSamuel Holland2022-07-101-18/+9
* | irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handlingSamuel Holland2022-07-011-1/+1
* | irqchip/sifive-plic: Add support for Renesas RZ/Five SoCLad Prabhakar2022-07-011-4/+74
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* Merge tag 'irqchip-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/maz...Thomas Gleixner2022-03-141-12/+26
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| * irqchip/sifive-plic: Disable S-mode IRQs if running in M-modeNiklas Cassel2022-03-021-5/+19
| * irqchip/sifive-plic: Improve naming scheme for per context offsetsNiklas Cassel2022-03-021-7/+7
* | irqchip/sifive-plic: Add missing thead,c900-plic match stringGuo Ren2022-02-021-0/+1
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* irqchip/sifive-plic: Fixup EOI failed when maskedGuo Ren2021-11-121-1/+7
* irqchip: Bulk conversion to generic_handle_domain_irq()Marc Zyngier2021-06-101-5/+3
* irqchip/sifive-plic: Mark two global variables __ro_after_initJisheng Zhang2021-04-071-2/+2
* irqchip/sifive-plic: Fix chip_data access within a hierarchyGreentime Hu2020-11-011-4/+4
* irqchip/sifive-plic: Fix broken irq_set_affinity() callbackGreentime Hu2020-10-251-1/+1
* irqchip: RISC-V per-HART local interrupt controller driverAnup Patel2020-06-091-9/+23
* RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel2020-06-091-15/+1
* irqchip/sifive-plic: Improve boot prints for multiple PLIC instancesAnup Patel2020-05-251-2/+2
* irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is presentAnup Patel2020-05-251-2/+12
* irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()Anup Patel2020-05-251-0/+3
* irqchip/sifive-plic: Remove incorrect requirement about number of irq contextsWesley W. Terpstra2020-05-181-2/+0
* irqchip/sifive-plic: Fix maximum priority threshold valueAtish Patra2020-04-171-1/+1
* irqchip/sifive-plic: Add support for multiple PLICsAtish Patra2020-03-161-30/+51
* irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineAtish Patra2020-03-161-4/+34
* Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/...Thomas Gleixner2020-01-241-4/+26
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| * irqchip/sifive-plic: Support irq domain hierarchyYash Shah2020-01-201-4/+26
* | riscv: prefix IRQ_ macro names with an RV_ namespacePaul Walmsley2020-01-041-1/+1
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* riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-4/+7
* Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/...Thomas Gleixner2019-10-251-2/+2
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| * irqchip/sifive-plic: Skip contexts except supervisor in plic_init()Alan Mikhak2019-10-251-2/+2
* | Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/...Thomas Gleixner2019-10-141-14/+15
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| * irqchip/sifive-plic: Switch to fasteoi flowMarc Zyngier2019-09-181-14/+15
* | irqchip/sifive-plic: set max threshold for ignored handlersChristoph Hellwig2019-09-051-2/+10
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* irqchip/sifive-plic: Implement irq_set_affinity() for SMP hostAnup Patel2019-02-211-6/+39
* irqchip/sifive-plic: Differentiate between PLIC handler and contextAnup Patel2019-02-211-8/+8
* irqchip/sifive-plic: Add warning in plic_init() if handler already presentAnup Patel2019-02-211-0/+5
* irqchip/sifive-plic: Pre-compute context hart base and enable baseAnup Patel2019-02-211-26/+21
* irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.Atish Patra2019-02-141-0/+5
* RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-221-3/+5
* RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-221-1/+1
* irqchip: add a SiFive PLIC driverChristoph Hellwig2018-08-131-0/+260
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