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path: root/drivers/media/i2c/ccs-pll.c
Commit message (Expand)AuthorAgeFilesLines
* media: ccs-pll: Initialise best_div to avoid a compiler warningSakari Ailus2023-08-101-1/+1
* Merge tag 'v5.11-rc6' into patchworkMauro Carvalho Chehab2021-02-011-7/+1
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| * media: ccs-pll: Fix link frequency for C-PHYSakari Ailus2021-01-071-7/+1
* | media: Revert "media: ccs-pll: Fix MODULE_LICENSE"Sakari Ailus2021-01-121-1/+1
* | media: ccs-pll: Switch from standard integer types to kernel onesSakari Ailus2021-01-121-57/+57
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* media: ccs-pll: Print pixel ratesSakari Ailus2020-12-071-0/+5
* media: ccs-pll: Add support for DDR OP system and pixel clocksSakari Ailus2020-12-071-20/+44
* media: ccs: Dual PLL supportSakari Ailus2020-12-071-2/+7
* media: ccs-pll: Add trivial dual PLL supportSakari Ailus2020-12-071-22/+195
* media: ccs-pll: Separate VT divisor limit calculation from the restSakari Ailus2020-12-071-27/+37
* media: ccs-pll: Fix VT post-PLL divisor calculationSakari Ailus2020-12-071-5/+7
* media: ccs-pll: Make VT divisors 16-bitSakari Ailus2020-12-071-26/+25
* media: ccs-pll: Rework bounds checksSakari Ailus2020-12-071-57/+91
* media: ccs-pll: Print relevant information on PLL treeSakari Ailus2020-12-071-19/+66
* media: ccs-pll: Better separate OP and VT sub-tree calculationSakari Ailus2020-12-071-23/+31
* media: ccs-pll: Check for derating and overrating, support non-derating sensorsSakari Ailus2020-12-071-29/+55
* media: ccs-pll: Split off VT subtree calculationSakari Ailus2020-12-071-124/+131
* media: ccs-pll: Add C-PHY supportSakari Ailus2020-12-071-9/+26
* media: ccs-pll: Add sanity checksSakari Ailus2020-12-071-0/+9
* media: ccs-pll: Add support flexible OP PLL pixel clock dividerSakari Ailus2020-12-071-7/+19
* media: ccs-pll: Support two cycles per pixel on OP domainSakari Ailus2020-12-071-6/+13
* media: ccs-pll: Add support for extended input PLL clock dividerSakari Ailus2020-12-071-1/+3
* media: ccs-pll: Add support for decoupled OP domain calculationSakari Ailus2020-12-071-15/+7
* media: ccs-pll: Add support for lane speed modelSakari Ailus2020-12-071-11/+25
* media: ccs-pll: Use explicit 32-bit unsigned typeSakari Ailus2020-12-071-2/+2
* media: ccs-pll: Fix check for PLL multiplier upper boundSakari Ailus2020-12-071-2/+1
* media: ccs-pll: Fix comment on check against maximum PLL multiplierSakari Ailus2020-12-071-1/+1
* media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchSakari Ailus2020-12-071-2/+9
* media: ccs-pll: Fix condition for pre-PLL divider lower boundSakari Ailus2020-12-071-1/+1
* media: ccs-pll: Begin calculation from OP system clock frequencySakari Ailus2020-12-071-8/+4
* media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYSakari Ailus2020-12-071-1/+1
* media: ccs-pll: Remove parallel bus supportSakari Ailus2020-12-071-5/+0
* media: ccs-pll: End search if there are no better values availableSakari Ailus2020-12-071-2/+8
* media: ccs-pll: Use correct VT divisor for calculating VT SYS divisorSakari Ailus2020-12-071-2/+2
* media: ccs-pll: Split limits and PLL configuration into front and back partsSakari Ailus2020-12-071-136/+146
* media: ccs-pll: Don't use div_u64 to divide a 32-bit numberSakari Ailus2020-12-071-1/+1
* media: ccs: Change my e-mail addressSakari Ailus2020-12-031-2/+2
* media: ccs-pll: Fix MODULE_LICENSESakari Ailus2020-12-031-1/+1
* media: smiapp-pll: Rename as ccs-pllSakari Ailus2020-12-031-0/+480
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