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path: root/drivers/mtd/spi-nor/core.c
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* mtd: spi-nor: sst: Add support for Global Unlock on sst26vfTudor Ambarus2021-02-051-1/+1
* mtd: spi-nor: Add Global Block Unlock commandTudor Ambarus2021-02-051-0/+37
* mtd: spi-nor: core: Add erase size check for erase command initializationTakahiro Kuwano2021-02-051-0/+1
* mtd: spi-nor: core: Fix erase type discovery for overlaid regionTakahiro Kuwano2021-02-051-4/+5
* mtd: spi-nor: keep lock bits if they are non-volatileMichael Walle2020-12-071-3/+20
* mtd: spi-nor: atmel: fix unlock_all() for AT25FS010/040Michael Walle2020-12-071-1/+1
* mtd: spi-nor: ignore errors in spi_nor_unlock_all()Michael Walle2020-12-071-10/+13
* mtd: spi-nor: core: Allow flashes to specify MTD writesizePratyush Yadav2020-12-071-1/+2
* mtd: spi-nor: Fix multiple typosJonathan Neuschäfer2020-12-071-2/+2
* mtd: spi-nor: core: disable Octal DTR mode on suspend.Pratyush Yadav2020-11-091-0/+15
* mtd: spi-nor: core: perform a Soft Reset on shutdownPratyush Yadav2020-11-091-0/+45
* mtd: spi-nor: core: enable octal DTR mode when possiblePratyush Yadav2020-11-091-0/+38
* mtd: spi-nor: Introduce SNOR_F_IO_MODE_EN_VOLATILETudor Ambarus2020-11-091-0/+3
* mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR modePratyush Yadav2020-11-091-2/+13
* mtd: spi-nor: core: use dummy cycle and address width info from SFDPPratyush Yadav2020-11-091-0/+10
* mtd: spi-nor: sfdp: parse xSPI Profile 1.0 tablePratyush Yadav2020-11-091-1/+1
* mtd: spi-nor: add support for DTR protocolPratyush Yadav2020-11-091-82/+237
* mtd: spi-nor: add spi_nor_controller_ops_{read_reg, write_reg, erase}()Pratyush Yadav2020-11-091-34/+53
* mtd: spi-nor: core: use EOPNOTSUPP instead of ENOTSUPPPratyush Yadav2020-11-091-5/+5
* mtd: spi-nor: Fix address width on flash chips > 16MBBert Vermeulen2020-10-281-3/+5
* mtd: spi-nor: Don't copy self-pointing struct aroundAlexander Sverdlin2020-10-281-3/+2
* Revert "mtd: spi-nor: Add capability to disable flash quad mode"Yicong Yang2020-09-141-36/+19
* Revert "mtd: spi-nor: Disable the flash quad mode in spi_nor_restore()"Yicong Yang2020-09-141-2/+0
* mtd: spi-nor: Disable the flash quad mode in spi_nor_restore()Yicong Yang2020-07-131-0/+2
* mtd: spi-nor: Add capability to disable flash quad modeYicong Yang2020-07-131-19/+36
* mtd: spi-nor: Fix SPI NOR acronymTudor Ambarus2020-05-281-2/+2
* mtd: spi-nor: Fix description of the sr_ready() return valueTudor Ambarus2020-04-291-4/+4
* mtd: spi-nor: Uniformize the return value in spi_nor_*_ready()Tudor Ambarus2020-04-291-1/+1
* mtd: spi-nor: core: fix kernel-doc typo for spi_nor_[{info|sfdp}_]init_params()Sergei Shtylyov2020-04-281-3/+3
* mtd: spi-nor: core: fix kernel-doc typo for spi_nor_manufacturer_init_params()Sergei Shtylyov2020-04-281-1/+1
* mtd: spi-nor: Add SR 4bit block protection supportJungseung Lee2020-03-241-18/+48
* mtd: spi-nor: Add generic formula for SR block protection handlingJungseung Lee2020-03-241-31/+41
* mtd: spi-nor: Set all BP bits to one when lock_len == mtd->sizeTudor Ambarus2020-03-241-7/+13
* mtd: spi-nor: Clear WEL bit when erase or program errors occurTudor Ambarus2020-03-231-0/+22
* mtd: spi-nor: Trim what is exposed in spi-nor.hTudor Ambarus2020-03-171-32/+54
* mtd: spi-nor: Drop the MFR definitionsTudor Ambarus2020-03-171-2/+0
* mtd: spi-nor: Get rid of the now empty spi_nor_ids[] tableBoris Brezillon2020-03-171-25/+0
* mtd: spi-nor: Move XMC bits out of core.cBoris Brezillon2020-03-171-3/+1
* mtd: spi-nor: Move Xilinx bits out of core.cBoris Brezillon2020-03-171-75/+1
* mtd: spi-nor: Move Catalyst bits out of core.cBoris Brezillon2020-03-171-7/+1
* mtd: spi-nor: Move Winbond bits out of core.cBoris Brezillon2020-03-171-114/+1
* mtd: spi-nor: Move SST bits out of core.cBoris Brezillon2020-03-171-120/+3
* mtd: spi-nor: Move Spansion bits out of core.cBoris Brezillon2020-03-171-58/+1
* mtd: spi-nor: Move Micron/ST bits out of core.cBoris Brezillon2020-03-171-120/+2
* mtd: spi-nor: Move Macronix bits out of core.cBoris Brezillon2020-03-171-68/+1
* mtd: spi-nor: Move ISSI bits out of core.cBoris Brezillon2020-03-171-65/+1
* mtd: spi-nor: Move Intel bits out of core.cBoris Brezillon2020-03-171-14/+1
* mtd: spi-nor: Move GigaDevice bits out of core.cBoris Brezillon2020-03-171-59/+1
* mtd: spi-nor: Move Fujitsu bits out of core.cBoris Brezillon2020-03-171-3/+1
* mtd: spi-nor: Move Everspin bits out of core.cBoris Brezillon2020-03-171-6/+1
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