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path: root/drivers/phy/cadence
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* phy: cadence-torrent: Remove unused `regmap` field from state structLars-Peter Clausen2022-07-081-1/+0
* phy: cadence: Sierra: Remove unused `regmap` field from state structLars-Peter Clausen2022-07-081-1/+0
* phy: cdns-dphy: Add support for DPHY TX on J721eRahul T R2022-07-051-0/+61
* phy: cdns-dphy: Add band config for dphy txRahul T R2022-07-051-1/+39
* phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configurationSwapnil Jakhade2022-04-131-3/+190
* phy: cadence: Add Cadence D-PHY Rx driverPratyush Yadav2022-03-023-0/+264
* phy/cadence: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)2022-02-251-6/+1
* phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju2022-02-071-25/+57
* phy: cadence: Sierra: fix error handling bugs in probe()Dan Carpenter2022-01-241-14/+21
* phy: cadence: Sierra: Add support for derived reference clock outputSwapnil Jakhade2021-12-271-1/+108
* phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade2021-12-271-1/+376
* phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade2021-12-271-8/+190
* phy: cadence: Sierra: Fix to get correct parent for mux clocksSwapnil Jakhade2021-12-271-5/+26
* phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade2021-12-271-1/+213
* phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade2021-12-271-1/+72
* phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade2021-12-271-0/+45
* phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade2021-12-271-0/+38
* phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ...Swapnil Jakhade2021-12-271-10/+11
* phy: cadence: Sierra: Add support to get SSC type from device treeSwapnil Jakhade2021-12-271-1/+5
* phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade2021-12-271-56/+139
* phy: cadence: Sierra: Use of_device_get_match_data() to get driver dataSwapnil Jakhade2021-12-271-9/+4
* phy: cadence-torrent: use swap() to make code cleanerYang Guang2021-11-231-4/+2
* phy: cadence-torrent: Add support to output received reference clockSwapnil Jakhade2021-10-261-11/+148
* phy: cadence-torrent: Model reference clock driver as a clock to enable deriv...Swapnil Jakhade2021-10-261-25/+132
* phy: cadence-torrent: Migrate to clk_hw based registration and OF APIsSwapnil Jakhade2021-10-261-11/+19
* phy: cadence-torrent: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade2021-08-171-1/+59
* phy: cadence-torrent: Add debug information for PHY configurationSwapnil Jakhade2021-08-171-4/+32
* phy: cadence-torrent: Add separate functions for reusable codeSwapnil Jakhade2021-08-171-18/+35
* phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clockSwapnil Jakhade2021-08-171-0/+162
* phy: cadence-torrent: Add PHY registers for DP in array formatSwapnil Jakhade2021-08-171-288/+334
* phy: cadence-torrent: Configure PHY registers as a function of input referenc...Swapnil Jakhade2021-08-171-408/+422
* phy: cadence-torrent: Add enum for supported input reference clock frequenciesSwapnil Jakhade2021-08-171-13/+38
* phy: cadence-torrent: Reorder few functions to remove function declarationsSwapnil Jakhade2021-08-171-619/+588
* phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK messageSwapnil Jakhade2021-08-171-12/+12
* phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()Wang Wensheng2021-05-311-0/+1
* phy: cadence-torrent: Add delay for PIPE clock to be stableKishon Vijay Abraham I2021-03-311-0/+9
* phy: cadence-torrent: Explicitly request exclusive reset controlKishon Vijay Abraham I2021-03-311-1/+1
* phy: cadence-torrent: Do not configure SERDES if it's already configuredKishon Vijay Abraham I2021-03-311-10/+22
* phy: cadence-torrent: Group reset APIs and clock APIsKishon Vijay Abraham I2021-03-311-31/+53
* phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocksKishon Vijay Abraham I2021-03-311-3/+37
* phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)Kishon Vijay Abraham I2021-03-312-3/+265
* phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I2021-03-311-0/+3
* phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I2021-03-311-10/+15
* phy: cadence-torrent: Use a common header file for Cadence SERDESKishon Vijay Abraham I2021-03-311-1/+1
* phy: cadence: Sierra: Explicitly request exclusive reset controlKishon Vijay Abraham I2021-03-311-2/+2
* phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I2021-03-311-11/+25
* phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I2021-03-311-22/+35
* phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I2021-03-311-0/+4
* phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I2021-03-311-1/+6
* phy: cadence-torrent: Update PCIe + USB config for correct PLL1 clockSwapnil Jakhade2021-03-301-16/+31
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