summaryrefslogtreecommitdiffstats
path: root/drivers/phy/cadence
Commit message (Expand)AuthorAgeFilesLines
* phy: cadence: convert to devm_platform_ioremap_resourceChunfeng Yun2020-11-163-9/+3
* phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configurationSwapnil Jakhade2020-09-181-0/+254
* phy: cadence-torrent: Add PCIe + USB multilink configurationSwapnil Jakhade2020-09-181-0/+216
* phy: cadence-torrent: Add single link USB register sequencesSwapnil Jakhade2020-09-181-1/+259
* phy: cadence-torrent: Add single link SGMII/QSGMII register sequencesSwapnil Jakhade2020-09-181-0/+89
* phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_valsSwapnil Jakhade2020-09-181-4/+18
* phy: cadence-torrent: Add PHY link configuration sequences for single linkSwapnil Jakhade2020-09-181-0/+44
* phy: cadence-torrent: Add clk changes for multilink configurationSwapnil Jakhade2020-09-181-24/+17
* phy: cadence-torrent: Update PHY reset for multilink configurationSwapnil Jakhade2020-09-181-7/+21
* phy: cadence-torrent: Add support for PHY multilink configurationSwapnil Jakhade2020-09-181-26/+757
* phy: cadence-torrent: Add PHY APB reset supportSwapnil Jakhade2020-09-181-0/+13
* phy: cadence-torrent: Check cmn_ready assertion during PHY power onSwapnil Jakhade2020-09-181-1/+30
* phy: cadence-torrent: Add single link PCIe supportSwapnil Jakhade2020-09-181-30/+266
* phy: cadence-torrent: Check total lane count for all subnodes is within limitSwapnil Jakhade2020-09-181-4/+15
* phy: cadence-torrent: Add separate regmap functions for torrent and DPSwapnil Jakhade2020-09-181-33/+66
* phy: cadence-torrent: Enable support for multiple subnodesSwapnil Jakhade2020-09-181-15/+0
* phy: cadence-torrent: Use devm_platform_ioremap_resource() to get reg addressesSwapnil Jakhade2020-09-181-6/+2
* phy: cadence-torrent: Use of_device_get_match_data() to get driver dataSwapnil Jakhade2020-09-181-8/+5
* phy: cadence: torrent: Constify regmap_config structsRikard Falkeborn2020-09-161-6/+6
* phy: cadence: salvo: Constify cdns_nxp_sequence_pairRikard Falkeborn2020-09-161-3/+3
* phy: cadence: Sierra: Constify static structsRikard Falkeborn2020-09-161-12/+12
* Merge branch 'topic/phy_attrs' into nextVinod Koul2020-09-161-0/+4
|\
| * phy: cadence-torrent: Set Torrent PHY attributesSwapnil Jakhade2020-09-161-0/+4
* | phy: cadence: salvo: Constify cdns_salvo_phy_opsRikard Falkeborn2020-08-311-1/+1
|/
* phy: cadence: salvo: fix wrong bit definitionPeter Chen2020-07-131-1/+1
* phy: cadence: sierra: Fix for USB3 U1/U2 stateSanket Parmar2020-05-181-13/+14
* phy: phy-cadence-salvo: add phy .init APIPeter Chen2020-05-151-1/+11
* phy: cadence: salvo: add salvo phy driverPeter Chen2020-05-073-0/+325
* phy: cadence-torrent: Add support for subnode bindingsSwapnil Jakhade2020-03-201-75/+217
* phy: cadence-torrent: Add platform dependent initialization structureSwapnil Jakhade2020-03-201-0/+9
* phy: cadence-torrent: Use regmap to read and write DPTX PHY registersSwapnil Jakhade2020-03-201-69/+100
* phy: cadence-torrent: Use regmap to read and write Torrent PHY registersSwapnil Jakhade2020-03-201-369/+650
* phy: cadence-torrent: Implement PHY configure APIsSwapnil Jakhade2020-03-201-5/+431
* phy: cadence-torrent: Add 19.2 MHz reference clock supportSwapnil Jakhade2020-03-201-17/+441
* phy: cadence-torrent: Refactor code for reusabilitySwapnil Jakhade2020-03-201-93/+137
* phy: cadence-torrent: Add wrapper for DPTX register accessSwapnil Jakhade2020-03-201-21/+50
* phy: cadence-torrent: Add wrapper for PHY register accessSwapnil Jakhade2020-03-201-65/+77
* phy: cadence-torrent: Adopt Torrent nomenclatureSwapnil Jakhade2020-03-201-53/+58
* phy: cadence-dp: Rename to phy-cadence-torrentYuti Amonkar2020-03-203-5/+5
* phy: cadence: Sierra: add phy_reset hookRoger Quadros2020-01-141-0/+10
* phy: cadence: Sierra: remove redundant initialization of pointer regmapColin Ian King2020-01-141-1/+1
* phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()Kishon Vijay Abraham I2020-01-081-1/+1
* phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to...Kishon Vijay Abraham I2020-01-081-0/+21
* phy: cadence: Sierra: Change MAX_LANES of Sierra to 16Kishon Vijay Abraham I2020-01-081-1/+21
* phy: cadence: Sierra: Check for PLL lock during PHY power onKishon Vijay Abraham I2020-01-081-1/+32
* phy: cadence: Sierra: Get reset control "array" for each linkKishon Vijay Abraham I2020-01-081-1/+1
* phy: cadence: Sierra: Configure both lane cdb and common cdb registers for ex...Anil Varughese2020-01-081-96/+254
* phy: cadence: Sierra: Modify register macro names to be in sync with Sierra u...Kishon Vijay Abraham I2020-01-081-83/+84
* phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_opsKishon Vijay Abraham I2020-01-081-6/+9
* phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoCKishon Vijay Abraham I2020-01-081-0/+14
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-20 18:35:34 +0000