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* phy: cadence-torrent: Add support to output received reference clockSwapnil Jakhade2021-10-261-11/+148
| | | | | | | | | | | Add support to output received reference clock. Model the received reference clock as an alternate parent of reference clock driver clock. When received refclk is selected to output on cmn_refclk_p/m, this is the internal reference clock driven on the pma_cmn_refclk_int. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210922123735.21927-5-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Model reference clock driver as a clock to enable ↵Swapnil Jakhade2021-10-261-25/+132
| | | | | | | | | | | | | | derived refclk When reference clock driver is enabled, either derived or received refclk is output on cmn_refclk_p/m. Update the reference clock driver implementation by modelling reference clock driver as a "clock" with derived reference clock set as its default parent. The support for received reference clock will be added in a separate patch. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210922123735.21927-4-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Migrate to clk_hw based registration and OF APIsSwapnil Jakhade2021-10-261-11/+19
| | | | | | | | | Use clk_hw based provider APIs to register clks to remove the usage of deprecated APIs. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210922123735.21927-2-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade2021-08-171-1/+59
| | | | | | | | | | PIPE PHY status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-10-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add debug information for PHY configurationSwapnil Jakhade2021-08-171-4/+32
| | | | | | | | | | Add debug information in probe regarding PHY configuration parameters like single link or multilink protocol along with number of lanes used for each protocol link. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-9-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add separate functions for reusable codeSwapnil Jakhade2021-08-171-18/+35
| | | | | | | | | | | Torrent PHY driver currently supports single link DP configuration. Prepare driver to support multilink DP configurations by adding separate functions for common initialization sequence. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210728145454.15945-8-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clockSwapnil Jakhade2021-08-171-0/+162
| | | | | | | | | Add PHY configuration registers for single link DP with 100MHz reference clock and NO_SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-7-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add PHY registers for DP in array formatSwapnil Jakhade2021-08-171-288/+334
| | | | | | | | | | Add PHY registers for single link DP in array format to simplify code and to improve readability. This supports already supported frequencies for DP of 19.2MHz and 25MHz. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-6-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Configure PHY registers as a function of input ↵Swapnil Jakhade2021-08-171-408/+422
| | | | | | | | | | | | | | reference clock rate Torrent PHY supports multiple serdes standards with different input reference clock frequencies. PHY register values differ based on the reference clock rate. Add PHY input reference clock frequency as a new dimension to select proper register configuration. No functional change is intended. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-5-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add enum for supported input reference clock frequenciesSwapnil Jakhade2021-08-171-13/+38
| | | | | | | | | | | Torrent PHY supports different input reference clock frequencies. Register configurations will be different based on reference clock value. Prepare driver to support such multiple reference clock frequencies. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210728145454.15945-4-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Reorder few functions to remove function declarationsSwapnil Jakhade2021-08-171-619/+588
| | | | | | | | | Reorder some functions to avoid function declarations. No functional change. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-3-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK messageSwapnil Jakhade2021-08-171-12/+12
| | | | | | | | | | | | Script checkpatch with --strict option gives message: CHECK: Avoid CamelCase: <REF_CLK_19_2MHz> CHECK: Avoid CamelCase: <REF_CLK_25MHz> Fix this by removing CamelCase usage. No functional change. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210728145454.15945-2-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()Wang Wensheng2021-05-311-0/+1
| | | | | | | | | | | Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: a43f72ae136a ("phy: cadence: Sierra: Change MAX_LANES of Sierra to 16") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wang Wensheng <wangwensheng4@huawei.com> Link: https://lore.kernel.org/r/20210517015749.127799-1-wangwensheng4@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add delay for PIPE clock to be stableKishon Vijay Abraham I2021-03-311-0/+9
| | | | | | | | | | | The Torrent spec specifies delay of 660.5us after phy_reset is asserted by the controller. To be on the safe side provide a delay of 5ms to 10ms in ->phy_on() callback where the SERDES is already configured in bootloader. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210330110138.24356-6-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Explicitly request exclusive reset controlKishon Vijay Abraham I2021-03-311-1/+1
| | | | | | | | | | | No functional change. Since the reset controls obtained in Torrent is exclusively used by the Torrent device, use exclusive reset control request API calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210330110138.24356-5-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Do not configure SERDES if it's already configuredKishon Vijay Abraham I2021-03-311-10/+22
| | | | | | | | | Do not configure torrent SERDES if it's already configured. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210330110138.24356-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Group reset APIs and clock APIsKishon Vijay Abraham I2021-03-311-31/+53
| | | | | | | | | | | No functional change intended. Group reset APIs and clock APIs in preparation for adding support to skip configuration if the SERDES is already configured by bootloader. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210330110138.24356-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocksKishon Vijay Abraham I2021-03-311-3/+37
| | | | | | | | | | | Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-14-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)Kishon Vijay Abraham I2021-03-312-3/+265
| | | | | | | | | | | | Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-13-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I2021-03-311-0/+3
| | | | | | | | | | | commit 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") enabled the clock in probe and failed to disable in remove callback. Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210319124128.13308-11-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I2021-03-311-10/+15
| | | | | | | | | | | | Instead of having separate structure members for each input clock, add an array for the input clocks within "struct cdns_sierra_phy". This is in preparation for adding more input clocks required for supporting additional clock combination. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-10-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Use a common header file for Cadence SERDESKishon Vijay Abraham I2021-03-311-1/+1
| | | | | | | | | | | | No functional change. In order to have a single header file for all Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is in preparation for adding Cadence Sierra SERDES specific macros. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210319124128.13308-9-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Explicitly request exclusive reset controlKishon Vijay Abraham I2021-03-311-2/+2
| | | | | | | | | | | No functional change. Since the reset controls obtained in Sierra is exclusively used by the Sierra device, use exclusive reset control request API calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-8-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I2021-03-311-11/+25
| | | | | | | | | | No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-7-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I2021-03-311-22/+35
| | | | | | | | | | No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-6-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I2021-03-311-0/+4
| | | | | | | | | | | | | Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I2021-03-311-1/+6
| | | | | | | | | | | | | | | Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Cc: <stable@vger.kernel.org> # v5.4+ Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Update PCIe + USB config for correct PLL1 clockSwapnil Jakhade2021-03-301-16/+31
| | | | | | | | | | Update PCIe + USB register sequences for correct PLL1 clock configuration. Also, update sequences for other USB configurations with dependent changes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1614838096-32291-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Update SGMII/QSGMII configuration specific to TIKishon Vijay Abraham I2021-03-301-14/+44
| | | | | | | | | Update SGMII/QSGMII configuration specific to TI. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1614838096-32291-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clockSwapnil Jakhade2021-03-301-28/+49
| | | | | | | | | | | | | | For PCIe + QSGMII configuration where QSGMII was using PLL1 and was expecting 10GHz clock, configuration was giving 8GHz clock. Update register sequences to get correct PLL1 configuration. Also, update single link PCIe and single link SGMII/QSGMII configurations with related changes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1614838096-32291-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add support to drive refclk outKishon Vijay Abraham I2021-03-302-3/+186
| | | | | | | | | | | | | | | cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210310120840.16447-7-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Fix error code in cdns_torrent_phy_probe()Dan Carpenter2021-01-131-0/+1
| | | | | | | | | | This error path should return -EINVAL, but currently it returns success. Fixes: d09945eacad0 ("phy: cadence-torrent: Check total lane count for all subnodes is within limit") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/X9s7Wxq+b6ls0q7o@mwanda Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: convert to devm_platform_ioremap_resourceChunfeng Yun2020-11-163-9/+3
| | | | | | | | | Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/1604642930-29019-4-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configurationSwapnil Jakhade2020-09-181-0/+254
| | | | | | | | Add USB + SGMII/QSGMII multilink configuration sequences. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-14-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add PCIe + USB multilink configurationSwapnil Jakhade2020-09-181-0/+216
| | | | | | | | Add PCIe + USB Unique SSC multilink configuration sequences. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-13-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add single link USB register sequencesSwapnil Jakhade2020-09-181-1/+259
| | | | | | | | Add support for single link USB configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-12-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add single link SGMII/QSGMII register sequencesSwapnil Jakhade2020-09-181-0/+89
| | | | | | | | Add support for single link SGMII/QSGMII configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-11-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_valsSwapnil Jakhade2020-09-181-4/+18
| | | | | | | | | Include PHY_PLL_CFG as a first register value to configure in link_cmn_vals array values. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-10-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add PHY link configuration sequences for single linkSwapnil Jakhade2020-09-181-0/+44
| | | | | | | | | Add support to configure link_cmn_vals and xcvr_diag_vals in case of single link PHY configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-9-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add clk changes for multilink configurationSwapnil Jakhade2020-09-181-24/+17
| | | | | | | | | Prepare and enable clock in probe instead of phy_init. Also, remove phy_exit callback. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-8-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Update PHY reset for multilink configurationSwapnil Jakhade2020-09-181-7/+21
| | | | | | | | | | For multilink configuration, deassert PHY and link reset after PHY registers are configured in probe and only check link status in power_on callback. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-7-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add support for PHY multilink configurationSwapnil Jakhade2020-09-181-26/+757
| | | | | | | | | | | | | Added support for multilink configuration of Torrent PHY. Currently, maximum two links are supported. In case of multilink configuration, PHY needs to be configured for both the protocols simultaneously at the beginning as per the requirement of Torrent PHY. Also, register sequences for PCIe + SGMII/QSGMII Unique SSC PHY multilink configurations are added. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-6-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add PHY APB reset supportSwapnil Jakhade2020-09-181-0/+13
| | | | | | | | Add support for PHY APB reset and make it optional. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Check cmn_ready assertion during PHY power onSwapnil Jakhade2020-09-181-1/+30
| | | | | | | | Check if cmn_ready is set after both PLL0 and PLL1 are locked. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add single link PCIe supportSwapnil Jakhade2020-09-181-30/+266
| | | | | | | | | Add single link PCIe register sequences in Torrent PHY driver. Also, add support for getting SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Check total lane count for all subnodes is within limitSwapnil Jakhade2020-09-181-4/+15
| | | | | | | | | Add checking if total number of lanes for all subnodes is not greater than number of lanes supported by PHY. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-6-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add separate regmap functions for torrent and DPSwapnil Jakhade2020-09-181-33/+66
| | | | | | | | | Added separate functions for regmap initialization of torrent PHY generic registers and DP specific registers. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Enable support for multiple subnodesSwapnil Jakhade2020-09-181-15/+0
| | | | | | | | | Enable support for multiple subnodes in torrent PHY to include multi-link combinations. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Use devm_platform_ioremap_resource() to get reg addressesSwapnil Jakhade2020-09-181-6/+2
| | | | | | | | | Use devm_platform_ioremap_resource() to get register addresses instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Use of_device_get_match_data() to get driver dataSwapnil Jakhade2020-09-181-8/+5
| | | | | | | | | Use of_device_get_match_data() to get driver data instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 12:45:30 +0000