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* phy: qcom: qmp-combo: Switch from V6 to V6 N4 register offsetsAbel Vesa2024-06-031-29/+160
| | | | | | | | | | | | | | | | | | | | Currently, none of the X1E80100 supported boards upstream have enabled DP. As for USB, the reason it is not broken when it's obvious that the offsets are wrong is because the only difference with respect to USB is the difference in register name. The V6 uses QPHY_V6_PCS_CDR_RESET_TIME while V6 N4 uses QPHY_V6_N4_PCS_RX_CONFIG. Now, in order for the DP to work, the DP serdes tables need to be added as they have different values for V6 N4 when compared to V6 ones, even though they use the same V6 offsets. While at it, switch swing and pre-emphasis tables to V6 as well. Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys") Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-3-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'phy-for-6.10' of ↵Linus Torvalds2024-05-211-3/+53
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull generic phy updates from Vinod Koul: "New HW Support: - Support for Embedded DisplayPort and DisplayPort submodes and driver support on Qualcomm X1E80100 edp driver - Qualcomm QMP UFS PHY for SM8475, QMP USB phy for QDU1000/QRU1000 and eusb2-repeater for SMB2360 - Samsung HDMI PHY for i.MX8MP, gs101 UFS phy - Mediatek XFI T-PHY support for mt7988 - Rockchip usbdp combo phy driver Updates: - Qualcomm x4 lane EP support for sa8775p, v4 ad v6 support for X1E80100, SM8650 tables for UFS Gear 4 & 5 and correct voltage swing tables - Freescale imx8m-pci pcie link-up updates - Rockchip rx-common-refclk-mode support - More platform remove callback returning void conversions" * tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits) dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180x dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: fix msm899[68] power-domains dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000 dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000 phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p phy: samsung-ufs: ufs: exit on first reported error phy: samsung-ufs: ufs: remove superfluous mfd/syscon.h header phy: rockchip: fix CONFIG_TYPEC dependency phy: rockchip: usbdp: fix uninitialized variable phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode phy: rockchip: add usbdp combo phy driver dt-bindings: phy: add rockchip usbdp combo phy document phy: add driver for MediaTek XFI T-PHY dt-bindings: phy: mediatek,mt7988-xfi-tphy: add new bindings phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5 MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101. ...
| * Merge branch 'fixes' into nextVinod Koul2024-04-121-3/+7
| |\ | | | | | | | | | | | | This brings rockchip,pcie3-phy changes into next which incoming patches are dependent on
| * | phy: qcom: qmp-combo: fix sm8650 voltage swing tableNeil Armstrong2024-04-051-1/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QMP USB3/DP PHY found in the SM8650 SoC requires a slightly different Voltage Swing table for HBR/RBR link speeds. Add a new hbr/rbr voltage switch table named "v6" used in a new sm8650 qmp_phy_cfg struct replacing the sm8550 fallback used for the sm8650 compatible. Fixes: 80c1afe8c5fe ("phy: qcom: qmp-combo: add QMP USB3/DP PHY tables for SM8650") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240226-topic-sm8650-upstream-combo-phy-swing-update-v1-1-08707ebca92a@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: qcom: qmp-combo: fix duplicate return in qmp_v4_configure_dp_phyNeil Armstrong2024-03-291-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove duplicate "return 0" in qmp_v4_configure_dp_phy() Fixes: 186ad90aa49f ("phy: qcom: qmp-combo: reuse register layouts for even more registers") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Link: https://lore.kernel.org/r/20240228-topic-sm8x50-upstream-phy-combo-fix-duplicate-return-v1-1-60027a37cab1@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | | phy: qcom: qmp-combo: fix VCO div offset on v5_5nm and v6Johan Hovold2024-04-121-0/+2
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 5abed58a8bde ("phy: qcom: qmp-combo: Fix VCO div offset on v3") fixed a regression introduced in 6.5 by making sure that the correct offset is used for the DP_PHY_VCO_DIV register on v3 hardware. Unfortunately, that fix instead broke DisplayPort on v5_5nm and v6 hardware as it failed to add the corresponding offsets also to those register tables. Fixes: 815891eee668 ("phy: qcom-qmp-combo: Introduce orientation variable") Fixes: 5abed58a8bde ("phy: qcom: qmp-combo: Fix VCO div offset on v3") Cc: stable@vger.kernel.org # 6.5: 5abed58a8bde Cc: Stephen Boyd <swboyd@chromium.org> Cc: Abhinav Kumar <quic_abhinavk@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Link: https://lore.kernel.org/r/20240408093023.506-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom: qmp-combo: Fix register base for QSERDES_DP_PHY_MODEStephen Boyd2024-04-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register base that was used to write to the QSERDES_DP_PHY_MODE register was 'dp_dp_phy' before commit 815891eee668 ("phy: qcom-qmp-combo: Introduce orientation variable"). There isn't any explanation in the commit why this is changed, so I suspect it was an oversight or happened while being extracted from some other series. Oddly the value being 0x4c or 0x5c doesn't seem to matter for me, so I suspect this is dead code, but that can be fixed in another patch. It's not good to write to the wrong register space, and maybe some other version of this phy relies on this. Cc: Douglas Anderson <dianders@chromium.org> Cc: Abhinav Kumar <quic_abhinavk@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Neil Armstrong <neil.armstrong@linaro.org> Cc: Abel Vesa <abel.vesa@linaro.org> Cc: Steev Klimaszewski <steev@kali.org> Cc: Johan Hovold <johan+linaro@kernel.org> Cc: Bjorn Andersson <quic_bjorande@quicinc.com> Cc: stable@vger.kernel.org # 6.5 Fixes: 815891eee668 ("phy: qcom-qmp-combo: Introduce orientation variable") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240405000111.1450598-1-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom: qmp-combo: Fix VCO div offset on v3Stephen Boyd2024-04-061-1/+5
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to setup clocks") changed the offset that is used to write to DP_PHY_VCO_DIV from QSERDES_V3_DP_PHY_VCO_DIV to QSERDES_V4_DP_PHY_VCO_DIV. Unfortunately, this offset is different between v3 and v4 phys: #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 meaning that we write the wrong register on v3 phys now. Add another generic register to 'regs' and use it here instead of a version specific define to fix this. This was discovered after Abhinav looked over register dumps with me from sc7180 Trogdor devices that started failing to light up the external display with v6.6 based kernels. It turns out that some monitors are very specific about their link clk frequency and if the default power on reset value is still there the monitor will show a blank screen or a garbled display. Other monitors are perfectly happy to get a bad clock signal. Cc: Douglas Anderson <dianders@chromium.org> Cc: Abhinav Kumar <quic_abhinavk@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to setup clocks") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240404234345.1446300-1-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'phy-for-6.9' of ↵Linus Torvalds2024-03-161-86/+25
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New hardware support: - Qualcomm X1E80100 PCIe phy support, SM8550 PCIe1 PHY, SC7180 UFS PHY and SDM630 USBC support - Rockchip HDMI/eDP Combo PHY driver - Mediatek MT8365 CSI phy driver Updates: - Rework on Qualcomm phy PCS registers and type-c handling - Cadence torrent phy updates for multilink configuration - TI gmii resume support" * tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits) phy: constify of_phandle_args in xlate phy: ti: tusb1210: Define device IDs phy: ti: tusb1210: Use temporary variable for struct device phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema phy: ti: gmii-sel: add resume support phy: mtk-mipi-csi: add driver for CSI phy dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5 phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink config for TI J7200 dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200 phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink configuration phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1 phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API dt-bindings: phy: qmp-ufs: Fix PHY clocks phy: qcom: sgmii-eth: move PCS registers to separate header phy: qcom: sgmii-eth: use existing register definitions phy: qcom: qmp-usbc: drop has_pwrdn_delay handling phy: qcom: qmp: move common bits definitions to common header phy: qcom: qmp: split DP PHY registers to separate headers ...
| * phy: constify of_phandle_args in xlateKrzysztof Kozlowski2024-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> #Broadcom Link: https://lore.kernel.org/r/20240217093937.58234-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom: qmp: move common bits definitions to common headerDmitry Baryshkov2024-01-301-21/+0
| | | | | | | | | | | | | | | | | | Move bit definitions for the common headers to the common phy-qcom-qmp.h header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-5-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom: qmp: split DP PHY registers to separate headersDmitry Baryshkov2024-01-301-1/+9
| | | | | | | | | | | | | | | | | | Split the DP PHY register definitions to separate headers, removing them from the global one. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-4-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom: qmp: move common functions to common headerDmitry Baryshkov2024-01-301-64/+16
| | | | | | | | | | | | | | | | Move common init tables code to the common header phy-qcom-qmp-common.h. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-3-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-combo: fix type-c switch registrationJohan Hovold2024-03-061-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to a long-standing issue in driver core, drivers may not probe defer after having registered child devices to avoid triggering a probe deferral loop (see fbc35b45f9f6 ("Add documentation on meaning of -EPROBE_DEFER")). Move registration of the typec switch to after looking up clocks and other resources. Note that PHY creation can in theory also trigger a probe deferral when a 'phy' supply is used. This does not seem to affect the QMP PHY driver but the PHY subsystem should be reworked to address this (i.e. by separating initialisation and registration of the PHY). Fixes: 2851117f8f42 ("phy: qcom-qmp-combo: Introduce orientation switching") Cc: stable@vger.kernel.org # 6.5 Cc: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240217150228.5788-7-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-combo: fix drm bridge registrationJohan Hovold2024-03-061-4/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to a long-standing issue in driver core, drivers may not probe defer after having registered child devices to avoid triggering a probe deferral loop (see fbc35b45f9f6 ("Add documentation on meaning of -EPROBE_DEFER")). This could potentially also trigger a bug in the DRM bridge implementation which does not expect bridges to go away even if device links may avoid triggering this (when enabled). Move registration of the DRM aux bridge to after looking up clocks and other resources. Note that PHY creation can in theory also trigger a probe deferral when a 'phy' supply is used. This does not seem to affect the QMP PHY driver but the PHY subsystem should be reworked to address this (i.e. by separating initialisation and registration of the PHY). Fixes: 35921910bbd0 ("phy: qcom: qmp-combo: switch to DRM_AUX_BRIDGE") Fixes: 1904c3f578dc ("phy: qcom-qmp-combo: Introduce drm_bridge") Cc: stable@vger.kernel.org # 6.5 Cc: Bjorn Andersson <quic_bjorande@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240217150228.5788-6-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'phy-for-6.8' of ↵Linus Torvalds2024-01-181-0/+174
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New Support: - Qualcomm SM8650 UFS, PCIe and USB/DP Combo PHY, eUSB2 PHY, SDX75 USB3, X1E80100 USB3 support - Mediatek MT8195 support - Rockchip RK3128 usb2 support - TI SGMII mode for J784S4 Updates: - Qualcomm v7 register offsets updates - Mediatek tphy support for force phy mode switch" * tag 'phy-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (34 commits) phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J784S4 phy: ti: gmii-sel: Enable SGMII mode for J784S4 phy: qcom-qmp-usb: Add Qualcomm X1E80100 USB3 PHY support dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add X1E80100 USB PHY binding phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document X1E80100 compatible dt-bindings: phy: qcom: snps-eusb2: Document the X1E80100 compatible phy: mediatek: tphy: add support force phy mode switch dt-bindings: phy: mediatek: tphy: add a property for force-mode switch phy: phy-can-transceiver: insert space after include phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: fix path to header phy: renesas: phy-rcar-gen2: use select for GENERIC_PHY phy: qcom-qmp: qserdes-txrx: Add v7 register offsets phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets phy: qcom-qmp: qserdes-com: Add v7 register offsets phy: qcom-qmp: pcs-usb: Add v7 register offsets phy: qcom-qmp: pcs: Add v7 register offsets phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets phy: qcom-qmp: qserdes-com: Add some more v6 register offsets ...
| * phy: qcom-qmp-combo: Add x1e80100 USB/DP combo physAbel Vesa2023-12-211-0/+170
| | | | | | | | | | | | | | | | | | | | The X1E80100 has three copies of an USB/DP compbo PHY, add support for this to the Qualcomm QMP PHY driver. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231201-x1e80100-phy-combo-v1-2-6938ec41f3ac@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom: qmp-combo: add QMP USB3/DP PHY tables for SM8650Neil Armstrong2023-11-161-0/+4
| | | | | | | | | | | | | | | | | | Add QMP USB3/DP Combo PHY support for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-7-a543a4c4b491@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom: qmp-combo: switch to DRM_AUX_BRIDGEDmitry Baryshkov2023-12-041-42/+2
|/ | | | | | | | | | Switch to using the new DRM_AUX_BRIDGE helper to create the transparent DRM bridge device instead of handcoding corresponding functionality. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231203114333.1305826-3-dmitry.baryshkov@linaro.org
* phy: qcom-qmp-combo: use v6 registers in v6 regs layoutDmitry Baryshkov2023-10-131-6/+6
| | | | | | | | Make sure that we use only v6 registers in qmp_v6_usb3phy_regs_layout. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230928105445.1210861-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: fix the prefix for the PCS_USB v6 registersDmitry Baryshkov2023-10-131-19/+19
| | | | | | | | | For all other generations, we have been using just the QPHY prefix for the PCS registers. Remove the _USB part of the QPHY_USB prefix. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230928105445.1210861-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: initialize PCS_USB registersKonrad Dybcio2023-09-211-0/+4
| | | | | | | | | | | | Currently, PCS_USB registers that have their initialization data in a pcs_usb_tbl table are never initialized. Fix that. Fixes: fc64623637da ("phy: qcom-qmp-combo,usb: add support for separate PCS_USB region") Reported-by: Adrien Thierry <athierry@redhat.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230829-topic-8550_usbphy-v3-2-34ec434194c5@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: Square out 8550 POWER_STATE_CONFIG1Konrad Dybcio2023-09-211-1/+1
| | | | | | | | | | | | | | | | There are two instances of the POWER_STATE_CONFIG1 register: one in the PCS space and another one in PCS_USB. The downstream init sequence pokes the latter one while we've been poking the former one (and misnamed it as the latter one, impostor!). Fix that up to avoid UB. Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550") Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230829-topic-8550_usbphy-v3-1-34ec434194c5@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: fix clock probingDmitry Baryshkov2023-08-221-6/+6
| | | | | | | | | | | | | | During rebase of qcom-qmp-combo series a call to devm_clk_bulk_get_all() got moved by git from qmp_combo_parse_dt_legacy() to phy_dp_clks_register(). This doesn't have any serious effect, since the clocks will be set in both legacy and non-legacy paths. However let's move it back to place anyway, to prevent the driver from fetching clocks twice. Fixes: 28e265bf84a8 ("phy: qcom-qmp-combo: simplify clock handling") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820235813.562284-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: add qcom,sc7280-qmp-usb3-dp-phy compat entryDmitry Baryshkov2023-07-241-0/+4
| | | | | | | | | Add separate device entry for Combo USB+DP QMP PHY on sc7280 platform. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230711120916.4165894-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: populate offsets for all combo PHYsDmitry Baryshkov2023-07-241-0/+8
| | | | | | | | | | In order to support newer style bindings for combo PHYs, populate offsets for all Combo QMP PHY configurations. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230711120916.4165894-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: simplify clock handlingDmitry Baryshkov2023-07-241-44/+23
| | | | | | | | | | | | For the existing PHYs for new binding we are going to drop ref_clk_src clock and always use ref clock. Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional() when new bindings are used and devm_clk_bulk_get_all() when legacy bindings are in place. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230711120916.4165894-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: Explicitly include correct DT includesRob Herring2023-07-171-1/+0
| | | | | | | | | | | | | | | | | | The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom: qmp-combo: extract common function to setup clocksDmitry Baryshkov2023-07-121-37/+26
| | | | | | | | | Extact qmp_combo_configure_dp_clocks(), a common function to setup PHY clocks depending on the selected link rate. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-8-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom: qmp-combo: drop qmp_v6_dp_aux_init()Dmitry Baryshkov2023-07-121-32/+12
| | | | | | | | | | The only difference between qmp_v6_dp_aux_init() and qmp_v4_dp_aux_init() is the address of COM_BIAS_EN_CLKBUFLR_EN register. Move it to register layout and drop the duplicate function. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-7-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom: qmp-combo: drop similar functionsDmitry Baryshkov2023-07-121-121/+2
| | | | | | | | | | The functions qmp_v5_configure_dp_phy() and qmp_v6_configure_dp_phy() are now copies of qmp_v4_configure_dp_phy(). Drop them and use the v4 function in all the cases. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom: qmp-combo: reuse register layouts for some more registersDmitry Baryshkov2023-07-121-12/+22
| | | | | | | | | | Use register layout for TX_HIGHZ_DRVR_EN and TX_TRANSCEIVER_BIAS_EN registers. This will allow us to unify qmp_v[456]_configure_dp_phy() functions in the next commit. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom: qmp-combo: reuse register layouts for even more registersDmitry Baryshkov2023-07-121-33/+71
| | | | | | | | | Instead of passing additional registers to qmp_combo_configure_dp_swing(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom: qmp-combo: reuse register layouts for more registersDmitry Baryshkov2023-07-121-36/+64
| | | | | | | | | Instead of passing additional registers to qmp_v456_configure_dp_phy(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom: qmp-combo: correct bias0_en programmingDmitry Baryshkov2023-07-121-2/+2
| | | | | | | | | | | | | | It seems the commit a2e927b0e50d ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") contained a typo for selecting bias0_en values. First, bias0_en and bias1_en are expected to be symmetrical, and then the vendor driver also uses `flipped : 0x3E : 0x15` statement for bias0_en. Correct bias0_en programming to follow this. Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550") Fixes: a2e927b0e50d ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: add support for the USB+DP PHY on SM8150 platformDmitry Baryshkov2023-07-121-0/+4
| | | | | | | | | SM8150 and SC8180X are close relatives. Reuse sc8180x data to support USB+DP combo PHY on SM8150 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230531023415.1209301-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom: qmp-combo: fix Display Port PHY configuration for SM8550Neil Armstrong2023-06-211-2/+6
| | | | | | | | | | | The SM8550 PHY also uses a different offset for the CMN_STATUS reg, use the right one for the v6 Display Port configuration. Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-phy-init-fix-v1-1-4e9da9f97991@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: Introduce drm_bridgeBjorn Andersson2023-05-191-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QMP combo PHY sits in an of_graph connected between the DisplayPort controller and a USB Type-C connector (or possibly a redriver). The TCPM needs to be able to convey the HPD signal to the DisplayPort controller, but no directly link is provided by DeviceTree so the signal needs to "pass through" the QMP combo phy. Handle this by introducing a drm_bridge which upon initialization finds the next bridge (i.e. the usb-c-connector) and chain this together. This way HPD changes in the connector will propagate to the DisplayPort driver. The connector bridge is resolved lazily, as the TCPM is expected to be able to resolve the typec mux and switch at probe time, so the QMP combo phy will probe before the TCPM. Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-7-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: Introduce orientation switchingBjorn Andersson2023-05-191-9/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The data lanes of the QMP PHY is swapped in order to handle changing orientation of the USB Type-C cable. Register a typec_switch device to allow a TCPM to configure the orientation. The newly introduced orientation variable is adjusted based on the request, and the initialized components are brought down and up again. To keep track of what parts needs to be cycled new variables to keep track of the individual init_count is introduced. Both the USB and the DisplayPort altmode signals are properly switched. For DisplayPort the controller will after the TCPM having established orientation power on the PHY, so this is not done implicitly, but for USB the PHY typically is kept initialized across the switch, and must therefore then be reinitialized. This is based on initial work by Wesley Cheng. Link: https://lore.kernel.org/r/20201009082843.28503-3-wcheng@codeaurora.org/ Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-6-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: Introduce orientation variableBjorn Andersson2023-05-191-24/+30
| | | | | | | | | | | | | | | | | | | | | In multiple places throughout the driver code has been written in prepration for handling of orientation switching. Introduce a typec_orientation in qmp_combo and fill out the various "placeholders" with the associated logic. By initializing the orientation to "normal" this change has no functional impact, but reduces the size of the upcoming introduction of dynamic orientation switching. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-5-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: Extend phy_mutex to all phy_opsBjorn Andersson2023-05-191-2/+19
| | | | | | | | | | | | | | The phy core ensures mutual exclusion across the ops for a given phy, but the upcoming introduction of USB Type-C orientation switching might race with the DisplayPort phy operations. So extend the mutual exclusion to cover the remaining ops as well, to avoid concurrent reconfiguration of the hardware. Reported-by: Johan Hovold <johan@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-4-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: Move phy_mutex out of com_init/exitBjorn Andersson2023-05-191-19/+28
| | | | | | | | | | | | | | | | | With the upcoming introduction of USB Type-C orientation switching the region of mutual exclusion needs to be extended to cover both the common init/exit as well as the individual functions. So move the phy_mutex one step up the stack. Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-3-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: fix init-count imbalanceJohan Hovold2023-05-081-2/+3
| | | | | | | | | | | | | | | | The init counter is not decremented on initialisation errors, which prevents retrying initialisation and can lead to the runtime suspend callback attempting to disable resources that have never been enabled. Add the missing decrement on initialisation errors so that the counter reflects the state of the device. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Cc: stable@vger.kernel.org # 4.12 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230502103810.12061-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: use qmp_combo_offsets_v3 instead of _v6Dmitry Baryshkov2023-03-311-17/+1
| | | | | | | | | | The qmp_combo_offsets_v3 table is already used for v3 and v4 PHYs. Reuse it for v6 too, dropping the separate qmp_combo_offsets_v6. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230323144726.1614344-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: fix v3 offsets tableDmitry Baryshkov2023-03-311-0/+1
| | | | | | | | | | | | | SM8350 and SM8450 use qmp_combo_offsets_v3 table, which doesn't have PCS_USB offset. Add the usb3_pcs_usb entry to program correct registers while setting up sm8350 and sm8450 USB+DP combo PHYs. Fixes: 05bd18348b88 ("phy: qcom-qmp-combo: Add config for SM6350") Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230323144726.1614344-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: Add support for SM8550Abel Vesa2023-02-101-7/+401
| | | | | | | | | Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208183421.2874423-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp: pcs-usb: Add v6 register offsetsAbel Vesa2023-02-101-0/+1
| | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom: com-qmp-combo: add SM8350 & SM8450 supportNeil Armstrong2023-02-101-0/+170
| | | | | | | | | | Copy the USB tables from the QMP USB3 PHY driver and add the missing DP tables from downstream to enable USB3/DP on the SM8350 and SM8450 platforms. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-2-ed849ae6b849@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: Add config for SM6350Luca Weiss2023-02-021-2/+137
| | | | | | | | | Add the tables and config for the combo phy found on SM6350. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230120-sm6350-usbphy-v4-2-4d700a90ba16@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-combo: rework regs layout arraysDmitry Baryshkov2023-01-181-12/+12
| | | | | | | | | | | | | Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212102.421491-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-22 01:13:28 +0000