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* phy: qcom: phy-qcom-snps-eusb2: Add support for eUSB2 repeaterNeil Armstrong2023-02-161-1/+18
| | | | | | | | | | | For USB 2.0 compliance, eUSB2 needs a repeater. The PHY needs to initialize and reset it. So add repeater support Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230208190200.2966723-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom: Add QCOM SNPS eUSB2 repeater driverAbel Vesa2023-02-163-0/+269
| | | | | | | | | | PM8550B contains a eUSB2 repeater used for making the eUSB2 from SM8550 USB 2.0 compliant. This can be modelled SW-wise as a Phy. So add a new phy driver for it. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208190200.2966723-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'phy-fixes-6.2' into nextVinod Koul2023-02-141-13/+0
|\ | | | | | | | | Merge fixes tag pulled into mainline by Linus into phy/next due to dependency on amlogic patches
| * phy: Revert "phy: qualcomm: usb28nm: Add MDM9607 init sequence"Marijn Suijten2023-01-131-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 557a28811c7e0286d3816842032db5eb7bb5f156. This commit introduced an init sequence from downstream DT [1] in the driver. As mentioned by the comment above the HSPHY_INIT_CFG macro for this sequence: /* * The macro is used to define an initialization sequence. Each tuple * is meant to program 'value' into phy register at 'offset' with 'delay' * in us followed. */ Instead of corresponding to offsets into the phy register, the sequence read by the downstream driver [2] is passed into ulpi_write [3] which crafts the address-value pair into a new value and writes it into the same register at USB_ULPI_VIEWPORT [4]. In other words, this init sequence is programmed into the hardware in a totally different way than downstream and is unlikely to achieve the desired result, if the hsphy is working at all. An alternative method needs to be found to write these init values at the desired location. Fortunately mdm9607 did not land upstream yet [5] and should have its compatible revised to use the generic one, instead of a compatible that writes wrong data to the wrong registers. [1]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/arch/arm/boot/dts/qcom/mdm9607.dtsi#585 [2]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/drivers/usb/phy/phy-msm-usb.c#4183 [3]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/drivers/usb/phy/phy-msm-usb.c#468 [4]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/drivers/usb/phy/phy-msm-usb.c#418 [5]: https://lore.kernel.org/linux-arm-msm/20210805222812.40731-1-konrad.dybcio@somainline.org/ Reported-by: Michael Srba <Michael.Srba@seznam.cz> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20221214223733.648167-1-marijn.suijten@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom: snps-eusb2: Add missing headersVinod Koul2023-02-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver was missing to include couple of headers explictly which causes build to fail on other archs drivers/phy/qualcomm/phy-qcom-snps-eusb2.c: In function 'qcom_snps_eusb2_hsphy_write_mask': drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:147:15: error: implicit declaration of function 'readl_relaxed' [-Werror=implicit-function-declaration] 147 | reg = readl_relaxed(base + offset); | ^~~~~~~~~~~~~ drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:150:9: error: implicit declaration of function 'writel_relaxed' [-Werror=implicit-function-declaration] 150 | writel_relaxed(reg, base + offset); | ^~~~~~~~~~~~~~ drivers/phy/qualcomm/phy-qcom-snps-eusb2.c: In function 'qcom_eusb2_default_parameters': drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:161:42: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] 161 | FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); | ^~~~~~~~~~ Fix this by adding bitfield.h and iopoll.h explictly Fixes: 80090810f5d3 ("phy: qcom: Add QCOM SNPS eUSB2 driver") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-combo: Add support for SM8550Abel Vesa2023-02-101-7/+401
| | | | | | | | | | | | | | | | | | Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208183421.2874423-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: Add v6 DP register offsetsAbel Vesa2023-02-101-0/+4
| | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6. Add the new DP specific offsets in the generic qmp header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: pcs-usb: Add v6 register offsetsAbel Vesa2023-02-102-0/+32
| | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom: Add QCOM SNPS eUSB2 driverAbel Vesa2023-02-103-0/+432
| | | | | | | | | | | | | | | | | | | | | | The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEsAbel Vesa2023-02-101-1/+343
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the SM8550 both g4 and g3 configurations. In addition, there is a new "lane shared" table that needs to be configured for g4, along with the No-CSR list of resets. The no-CSR allows resetting the PHY without actually dropping the PHY configuration. The no-CSR needs to be deasserted only after the PHY has been configured and the PLL has stabilized. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208180020.2761766-9-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsetsAbel Vesa2023-02-102-0/+33
| | | | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-8-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsetsAbel Vesa2023-02-102-0/+46
| | | | | | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new qserdes TX RX PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: pcs-pcie: Add v6.20 register offsetsAbel Vesa2023-02-102-0/+24
| | | | | | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: pcs-pcie: Add v6 register offsetsAbel Vesa2023-02-102-0/+16
| | | | | | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: pcs: Add v6.20 register offsetsAbel Vesa2023-02-102-0/+20
| | | | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-4-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: pcs: Add v6 register offsetsAbel Vesa2023-02-102-0/+18
| | | | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom: com-qmp-combo: add SM8350 & SM8450 supportNeil Armstrong2023-02-101-0/+170
| | | | | | | | | | | | | | | | | | | | Copy the USB tables from the QMP USB3 PHY driver and add the missing DP tables from downstream to enable USB3/DP on the SM8350 and SM8450 platforms. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-2-ed849ae6b849@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: Introduce Kconfig symbols for discrete driversStephen Boyd2023-02-032-10/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a config option for each QMP PHY driver now that the QMP PHY mega-driver has been split up into different modules. This allows kernel configurators to limit the binary size of the kernel by only compiling in the QMP PHY driver that they need. Leave the old config QCOM_QMP in place and make it into a menuconfig so that 'make olddefconfig' continues to work. Furthermore, set the default of the new Kconfig symbols to be QCOM_QMP so that the transition is smooth. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20230202215330.2152726-1-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-combo: Add config for SM6350Luca Weiss2023-02-021-2/+137
| | | | | | | | | | | | | | | | | | Add the tables and config for the combo phy found on SM6350. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230120-sm6350-usbphy-v4-2-4d700a90ba16@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Add SM8550 supportAbel Vesa2023-02-021-0/+96
| | | | | | | | | | | | | | | | | | | | Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230117224148.1914627-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: pcs-ufs: Add v6 register offsetsAbel Vesa2023-02-022-0/+32
| | | | | | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230117224148.1914627-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register offsetsAbel Vesa2023-02-022-0/+32
| | | | | | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230117224148.1914627-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: qserdes-txrx: Add v6 register offsetsAbel Vesa2023-02-022-0/+78
| | | | | | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230117224148.1914627-4-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: qserdes-com: Add v6 register offsetsAbel Vesa2023-02-022-0/+84
| | | | | | | | | | | | | | | | | | | | | | The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230117224148.1914627-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-usb: fix the regs layout table for sdx65 uniphy PHYDmitry Baryshkov2023-01-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The sdx64 uniphy gen3x1 PHY references the qmp_v4_usb3phy_regs_layout while the PHY itself uses v5 regs. While there are only minor differences between v4 and v5 regs and none of them concerns registers mentions in regs_layout, switch the PHY to use qmp_v5_usb3phy_regs_layout, to remove possible confusion. Fixes: 14d98d3bf70e ("phy: qcom-qmp-usb: fix regs layout arrays") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212138.421583-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-pcie: fix the regs layout table for sm8450 gen3x1 PHYDmitry Baryshkov2023-01-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The sm8450 gen3x1 PHY references the pciephy_v4_regs_layout while the PHY itself uses v5 regs. While there are only minor differences between v4 and v5 regs and none of them concerns registers mentions in regs_layout, switch the PHY to use pciephy_v5_regs_layout to remove possible confusion. Fixes: bbe207a1aba1 ("phy: qcom-qmp-pcie: rename regs layout arrays") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212138.421583-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-combo: rework regs layout arraysDmitry Baryshkov2023-01-181-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212102.421491-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-combo: remove QPHY_PCS_LFPS_RXTERM_IRQ_STATUS regDmitry Baryshkov2023-01-181-5/+0
| | | | | | | | | | | | | | | | | | The QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212102.421491-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qualcomm: qmp-ufs: rename qmp_ufs_offsets_v5 to qmp_ufs_offsetsDmitry Baryshkov2023-01-181-3/+3
| | | | | | | | | | | | | | | | | | | | All currently known QMP UFS PHYs have the same offsets for register sub-regions. Instead of using qmp_ufs_offsets_v5 for older generations of PHYs, rename the offsets struct instance to remove _v5 suffix. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113195515.407866-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoCManivannan Sadhasivam2023-01-171-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-13-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoCManivannan Sadhasivam2023-01-171-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-12-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoCManivannan Sadhasivam2023-01-171-0/+36
| | | | | | | | | | | | | | | | | | | | | | UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-11-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Avoid setting HS G3 specific registersManivannan Sadhasivam2023-01-171-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SM8350 default init sequence sets some PCS registers to HS G3, thereby disabling HS G4 mode. This has the effect on MPHY capability negotiation between the host and the device during link startup and causes the PA_MAXHSGEAR to G3 irrespective of device max gear. Due to that, the agreed gear speed determined by the UFS core will become G3 only and the platform won't run at G4. So, let's remove setting these registers for SM8350 as like other G4 compatible platforms. One downside of this is that, when the board design uses non-G4 compatible device, then MPHY will continue to run in the default mode (G4) even if UFSHCD runs in G3. But this is the case for other platforms as well. Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-10-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoCManivannan Sadhasivam2023-01-172-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-9-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoCManivannan Sadhasivam2023-01-171-0/+36
| | | | | | | | | | | | | | | | | | | | | | UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-8-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_bManivannan Sadhasivam2023-01-171-5/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since now there is support for configuring the HS Rate B mode properly, let's move the register setting to tbls_hs_b struct for all SoCs. This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-7-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 modeManivannan Sadhasivam2023-01-171-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Add separate tables_hs_g4 instance to allow the PHY driver to configure the PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and PCS register setting in tables_hs_g4 and the UFS driver can request the Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-6-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B modeManivannan Sadhasivam2023-01-171-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-5-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls structManivannan Sadhasivam2023-01-171-83/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tbls. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-4-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Rename MSM8996 PHY definitionsManivannan Sadhasivam2023-01-171-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's rename all of the definitions to use "_ufsphy_". Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitionsManivannan Sadhasivam2023-01-171-73/+73
| | | | | | | | | | | | | | | | | | | | | | | | Following the other QMP PHY drivers like PCIe, let's remove the "_tbl" suffix from the qmp_phy_init_tbl definitions. This helps in maintaining the uniformity across all of the QMP PHY drivers. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-2-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: Add SM6125 UFS PHY supportLux Aliaga2023-01-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | The SM6125 UFS PHY is compatible with the one from SM6115. Add a compatible for it and modify the config from SM6115 to make them compatible with the SC8280XP binding Signed-off-by: Lux Aliaga <they@mint.lgbt> Reviewed-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20230108195336.388349-4-they@mint.lgbt Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-usb: Add Qualcomm SM6115 / SM4250 USB3 PHY supportBhupesh Sharma2023-01-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | Enable SM6115 / SM4250 USB3 PHY support by adding the qmp_phy_cfg data. Since this PHY is the same as the one used on QCM2290, reuse the QCM2290 qmp_phy_cfg data already available. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20221213122843.454845-4-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-usb: Fix QSERDES_V3_RX_UCDR_PI_CONTROLS init valBhupesh Sharma2023-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As per the Qualcomm QMP v3 PHY programming guide document, QSERDES_V3_RX_UCDR_PI_CONTROLS configuration should be set to an initial configuration value of 0x80. Fix the same. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20221213122843.454845-3-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: move type-specific headers to particular driverDmitry Baryshkov2023-01-125-14/+17
| | | | | | | | | | | | | | | | | | | | Remove QMP PHY type-specific headers inclusion from the common header and move them to the specific PHY drivers to cleanup the namespaces used by different drivers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-14-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-usb: fix regs layout arraysDmitry Baryshkov2023-01-121-11/+13
| | | | | | | | | | | | | | | | | | | | Drop qcm2290_usb3phy_regs_layout, it is a duplicate of qmp_v3_usb3phy_regs_layout. Introduce qmp_v5_usb3phy_regs_layout to be used for sm8350 and sc8280xp. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-13-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-usb: rework regs layout arraysDmitry Baryshkov2023-01-122-26/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-12-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-usb: remove QPHY_PCS_MISC_TYPEC_CTRL regDmitry Baryshkov2023-01-121-3/+0
| | | | | | | | | | | | | | | | | | The QPHY_PCS_MISC_TYPEC_CTRL register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-11-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-usb: remove QPHY_PCS_LFPS_RXTERM_IRQ_STATUS regDmitry Baryshkov2023-01-122-6/+1
| | | | | | | | | | | | | | | | | | The QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-10-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-ufs: rename regs layout arraysDmitry Baryshkov2023-01-122-16/+21
| | | | | | | | | | | | | | | | Rename regs layouts to follow the QMP PHY version. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-9-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-13 23:39:02 +0000