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* pinctrl: single: use of_device_get_match_data() to get soc dataMasahiro Yamada2017-05-291-6/+2
| | | | | | | | | Use of_device_get_match_data() instead of of_match_device(). It allows us to remove the forward declaration of pcs_of_match. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zte: fix group_desc initializationShawn Guo2017-05-291-2/+2
| | | | | | | | | | | | | | | There are a couple of issues with group_desc initialization in function zx_pinctrl_build_state(). - num_pins is not initialized and remains zero. - pins shouldn't be initialized with a pointer to variable in the stack. With them fixed, pin_request() in pinmux_enable_setting() can be invoked correctly. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxbb: Add SPI pins for SPICC controllerNeil Armstrong2017-05-291-0/+14
| | | | | | | | The SPICC controller has dedicated SPI pins, this patchs add the pins definition in the GXBB pinctrl driver Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxl: Add SPI pins for the SPICC controllerNeil Armstrong2017-05-291-0/+14
| | | | | | | | The SPICC controller has dedicated SPI pins, this patchs add the pins definition in the GXL pinctrl driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Fix SPDIF function name for A83TChen-Yu Tsai2017-05-231-1/+1
| | | | | | | | | | | | | We use well known standard names for functions that have name, such as I2C, SPI, SPDIF, etc.. Fix the function name of SPDIF, which was named OWA (One Wire Audio) based on Allwinner datasheets. Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'mcp23s08' into develLinus Walleij2017-05-233-0/+1208
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| * pinctrl: mcp23s08: drop comment about missing irq supportSebastian Reichel2017-05-231-17/+2
| | | | | | | | | | | | | | | | The driver supports using mcp23xxx as interrupt controller, so let's drop all comments stating otherwise. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: simplify spi_present_mask handlingSebastian Reichel2017-05-231-19/+10
| | | | | | | | | | Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: generalize irq property handlingSebastian Reichel2017-05-231-18/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves irq property handling from spi/i2c specific code into the generic mcp23s08_probe_one. This is possible because the device properties are named equally. As a side-effect this drops support for setting the properties via pdata, which has no mainline users. If boardcode wants to enable the chip as interrupt controller it can attach the device properties instead. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: simplify spi pdata handlingSebastian Reichel2017-05-231-35/+32
| | | | | | | | | | | | | | | | Simplify spi pdata handling, so that it uses pdata when available and falls back to reading device properties otherwise. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: simplify i2c pdata handlingSebastian Reichel2017-05-231-19/+7
| | | | | | | | | | | | | | | | Simplify i2c pdata handling, so that it uses pdata when available and falls back to reading device properties otherwise. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: switch to devm_gpiochip_add_dataSebastian Reichel2017-05-231-38/+2
| | | | | | | | | | | | | | | | Switching to devm_gpiochip_add_data simplifies the driver's cleanup routine and safes a few loc. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: use managed kzalloc for mcpSebastian Reichel2017-05-231-8/+2
| | | | | | | | | | | | | | | | Let's remove a few lines of code by using managed memory for mcp variable. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: irq mapping is already doneSebastian Reichel2017-05-231-4/+0
| | | | | | | | | | | | | | | | i2c-core and spi-core already assign the irq, so we can drop the additional call from the mcp driver. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: drop OF_GPIO dependencySebastian Reichel2017-05-231-1/+0
| | | | | | | | | | | | | | | | The driver compiles & works perfectly fine without OF_GPIO on x86, so lets drop the dependency. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: switch to regmap cachingSebastian Reichel2017-05-231-95/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using custom caching, this switches to regmap based caching. Before the conversion the debugfs file used uncached values, so that it was easily possible to see power-loss related problems. The new code will check and recover at this place. The patch will also ensure, that irqs are not cleared by checking register status in debugfs. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: drop pullup config from pdataSebastian Reichel2017-05-231-7/+0
| | | | | | | | | | | | | | | | | | mcp23s08 support configuration of the pullups using the pinconf framework. This removes the custom pullup configuration from platform data, which has no upstream users. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: add pinconf supportSebastian Reichel2017-05-232-24/+176
| | | | | | | | | | | | | | | | | | mcp23xxx device have configurable 100k pullup resistors. This adds support for enabling them using pinctrl's pinconf interface. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * gpio: mcp23s08: move to pinctrlSebastian Reichel2017-05-233-0/+1061
| | | | | | | | | | | | | | | | | | | | This moves the mcp23s08 driver from gpio to pinctrl. Actual pinctrl support for configuration of the pull-up resistors follows in its own patch. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge branch 'ingenic' into develLinus Walleij2017-05-223-0/+862
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| * | pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCsPaul Cercueil2017-05-223-0/+862
| |/ | | | | | | | | | | | | | | This driver handles pin configuration and pin muxing for the JZ4740 and JZ4780 SoCs from Ingenic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: When claiming hog, skip maps not served by same deviceNikita Yushchenko2017-05-221-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When pinctrl device registers, it automatically claims hogs, that is, maps that pinctrl device serves for itself. It is possible that in addition to SoC's pinctrl device, other pinctrl devices get registered. E.g. some gpio expander devies are registered as pinctrl devices. For such devices, pinctrl maps could be defined that set up SoC's pins (e.g. interrupt pin for gpio expander). Such a map will have target device set to gpio expander. Here is device tree snippet that causes this scenario: &i2c0 { sx1503@20 { compatible = "semtech,sx1503q"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sx1503_20>; ... }; }; ... &iomuxc { pinctrl_sx1503_20: pinctrl-sx1503-20 { fsl,pins = < VF610_PAD_PTB1__GPIO_23 0x219d >; }; }; Such a map will have target device set to gpio expander. However is not a hog, it is a regular map that is claimed by core before gpio expander device is probed. Thus when looking for hogs, it is not enough to check that map's target device is set to pinctrl device being registered. Need also check that map's control device is also set to the same. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: add soc specific mux_mode mask and shift propertyDong Aisheng2017-05-223-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support. One trick in exist code that Vybrid hardcoded the config part as 0xffff because its mux_config register BIT[15-0] are all configs part. But it's not true in ULP, so use mux_mask instead to address the difference. Cc: Stefan Agner <stefan@agner.ch> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: add generic pin config core supportDong Aisheng2017-05-223-11/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform. Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently. In order to cope with some special case, a platform specific fixup() function is also available to use. Note that rather than fully utilizing the generic pinconf support provided by pinctrl core, IMX only adopts the device tree bindings of generic pinconf. The config used in .pin_config_get[set] are raw register data instead of generic one which makes us align the exist using. And that's also why we cannot set pinconf_ops.is_generic. Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG caseDong Aisheng2017-05-221-4/+8
| | | | | | | | | | | | | | | | | | | | The original implemented debug message does not work for SHARE_MUX_CONF_REG case. This patch fixes it. Fixes: bf5a530971af ("pinctrl: imx: add VF610 support to imx pinctrl framework") Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: Check for memory allocation failureChristophe JAILLET2017-05-221-2/+3
| | | | | | | | | | | | | | | | | | | | If 'devm_kzalloc' fails, a NULL pointer will be dereferenced. Return -ENOMEM instead, as done for the other memory allocation just a few lines below. BTW, change the 'devm_kzalloc' into a 'devm_kcalloc'. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mediatek: reuse pinctrl driver for mt7623Sean Wang2017-05-225-2324/+2
| | | | | | | | | | | | | | | | | | | | | | mt7623 pinctrl hardware can be compatible with mt2701 driver, so the patch lets the pinctrl on mt7623 SoC reuse the driver and deletes those redundant ones. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Acked-by: John Crispin <john@phrozen.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8: add the AO HDMI CEC pinMartin Blumenstingl2017-05-221-0/+9
| | | | | | | | | | | | | | | | This adds another missing pin found in the Meson8 SoCs. Currently there's no driver which would use this pin yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8: add support for the AO remote output pinMartin Blumenstingl2017-05-221-1/+3
| | | | | | | | | | | | | | | | This adds another missing pin found in the Meson8 SoCs. Currently there's no driver which would use this pin yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8: add support for the I2S and SPDIF pinsMartin Blumenstingl2017-05-221-0/+52
| | | | | | | | | | | | | | | | This adds support for the I2S and SPDIF input and output pins, similar to what we have on GXBB and GXL. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8: add the PWM pinsMartin Blumenstingl2017-05-221-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds the missing pins for the PWM controllers found in Amlogic Meson8 SoCs. This includes the pins for PWM_A, PWM_B, PWM_C, PWM_D, PWM_E and PWM_F controllers. There is an additional PWM function with the name PWM_VS in the vendor kernel sources which seems to be used for external video input. Thus it's not part of this change as the IP block behind the pwm-meson driver is not responsible for these pins. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Adjust nine checks for null pointersMarkus Elfring2017-05-221-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The script “checkpatch.pl” pointed information out like the following. Comparison to NULL could be written … Thus fix the affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Use seq_putc() in pinctrl_maps_show()Markus Elfring2017-05-221-1/+1
| | | | | | | | | | | | | | | | | | | | A single character (line break) should be put into a sequence. Thus use the corresponding function "seq_putc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Add spaces for better code readabilityMarkus Elfring2017-05-221-4/+4
| | | | | | | | | | | | | | | | | | | | | | The script "checkpatch.pl" pointed information out like the following. CHECK: spaces preferred around that '+' (ctx:VxV) Thus fix the affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Combine substrings for a message in pin_config_group_get()Markus Elfring2017-05-221-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | The script "checkpatch.pl" pointed information out like the following. WARNING: quoted string split across lines Thus fix the affected source code place. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Adjust five checks for null pointersMarkus Elfring2017-05-221-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The script “checkpatch.pl” pointed information out like the following. Comparison to NULL could be written !… Thus fix the affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Replace two seq_printf() calls by seq_puts() in pinconf_show_map()Markus Elfring2017-05-221-2/+2
| | | | | | | | | | | | | | | | | | | | Strings which did not contain data format specifications should be put into a sequence. Thus use the corresponding function "seq_puts". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/amd: Update contact information for AMD pinctrl/amdShyam Sundar S K2017-05-221-0/+4
| | | | | | | | | | | | | | | | | | Updating the point of contact for AMD GPIO driver. Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Signed-off-by: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> Cc: Ken Xue <Ken.Xue@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Use seq_putc() in three functionsMarkus Elfring2017-05-221-5/+3
| | | | | | | | | | | | | | | | | | | | A single character (line break) should be put into a sequence. Thus use the corresponding function "seq_putc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: armada-37xx: Add irqchip supportGregory CLEMENT2017-05-221-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada 37xx SoCs can handle interrupt through GPIO. However it can only manage the edge ones. The way the interrupt are managed is classical so we can use the generic interrupt chip model. The only unusual "feature" is that many interrupts are connected to the parent interrupt controller. But we do not take advantage of this and use the chained irq with all of them. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: rockchip: remove unneeded (void *) casts in of_match_tableMasahiro Yamada2017-05-221-11/+11
| | | | | | | | | | | | | | | | of_device_id::data is an opaque pointer. No explicit cast is needed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: add ZTE ZX pinctrl driver supportShawn Guo2017-05-227-0/+1594
|/ | | | | | | | | | | | | | | | | | | | | | The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of a main controller and an auxiliary one. For example, on ZX296718 SoC, the main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both controllers work together to control pin multiplexing and configuration. For most of pins, the pinmux function is controlled by main controller only, and this type of pins are meant by term 'TOP pins'. For other pins, the pinmux is controlled by both main and auxiliary controllers, as the available multiplexing functions for the pin spread in both controllers. This type of pins are called 'AON pins'. Though pinmux implementation is quite different, pinconf is same for both types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG on ZX296718. The patch adds the ZTE ZX core pinctrl driver to support this hybrid pin controller as well as ZX296718 SoC specific pin data. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'for-linus' of ↵Linus Torvalds2017-05-021-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial Pull trivial tree updates from Jiri Kosina. * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: tty: fix comment for __tty_alloc_driver() init/main: properly align the multi-line comment init/main: Fix double "the" in comment Fix dead URLs to ftp.kernel.org drivers: Clean up duplicated email address treewide: Fix typo in xml/driver-api/basics.xml tools/testing/selftests/powerpc: remove redundant CFLAGS in Makefile: "-Wall -O2 -Wall" -> "-O2 -Wall" selftests/timers: Spelling s/privledges/privileges/ HID: picoLCD: Spelling s/REPORT_WRTIE_MEMORY/REPORT_WRITE_MEMORY/ net: phy: dp83848: Fix Typo UBI: Fix typos Documentation: ftrace.txt: Correct nice value of 120 priority net: fec: Fix typo in error msg and comment treewide: Fix typos in printk
| * treewide: Fix typos in printkMasanari Iida2017-03-241-1/+1
| | | | | | | | | | | | | | | | | | | | This patch fix some spelling typos found in printk. [jkosina@suse.cz: drop arch/arm64/kernel/hibernate.c that was already in place] Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | Merge tag 'pinctrl-v4.12-1' of ↵Linus Torvalds2017-05-0260-3911/+11456
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.12 cycle. The extra week before the merge window actually resulted in some of the type of fixes that usually arrive after the merge window already starting to trickle in from eager developers using -next, I'm impressed. I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal with the onset of Samsung patches. It works great. Apart from that it is a boring round, just incremental updates and fixes all over the place, no serious core changes or anything exciting like that. The most pleasing to see is Julia Cartwrights work to audit the irqchip-providing drivers for realtime locking compliance. It's one of those "I should really get around to looking into that" things that have been on my TODO list since forever. Summary: Core changes: - add bi-directional and output-enable pin configurations to the generic bindings and generic pin controlling core. New drivers or subdrivers: - Armada 37xx SoC pin controller and GPIO support. - Axis ARTPEC-6 SoC pin controller support. - AllWinner A64 R_PIO controller support, and opening up the AllWinner sunxi driver for ARM64 use. - Rockchip RK3328 support. - Renesas R-Car H3 ES2.0 support. - STM32F469 support in the STM32 driver. - Aspeed G4 and G5 pin controller support. Improvements: - a whole slew of realtime improvements to drivers implementing irqchips: BCM, AMD, SiRF, sunxi, rockchip. - switch meson driver to get the GPIO ranges from the device tree. - input schmitt trigger support on the Rockchip driver. - enable the sunxi (AllWinner) driver to also be used on ARM64 silicon. - name the Qualcomm QDF2xxx GPIO lines. - support GMMR GPIO regions on the Intel Cherryview. This fixes a serialization problem on these platforms. - pad retention support for the Samsung Exynos 5433. - handle suspend-to-ram in the AT91-pio4 driver. - pin configuration support in the Aspeed driver. Cleanups: - the final name of Rockchip RK1108 was RV1108 so rename the driver and variables to stay consistent" * tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits) pinctrl: mediatek: Add missing pinctrl bindings for mt7623 pinctrl: artpec6: Fix return value check in artpec6_pmx_probe() pinctrl: artpec6: Remove .owner field for driver pinctrl: tegra: xusb: Silence sparse warnings ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller" pinctrl: make artpec6 explicitly non-modular pinctrl: aspeed: g5: Add pinconf support pinctrl: aspeed: g4: Add pinconf support pinctrl: aspeed: Add core pinconf support pinctrl: aspeed: Document pinconf in devicetree bindings pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl pinctrl: stm32: Add STM32F469 MCU support Documentation: dt: Remove ngpios from stm32-pinctrl binding pinctrl: stm32: replace device_initcall() with arch_initcall() pinctrl: stm32: add possibility to use gpio-ranges to declare bank range pinctrl: armada-37xx: Add gpio support pinctrl: armada-37xx: Add pin controller support for Armada 37xx pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers pinctrl: core: Make pinctrl_init_controller() static pinctrl: generic: Add bi-directional and output-enable ...
| * | pinctrl: artpec6: Fix return value check in artpec6_pmx_probe()Wei Yongjun2017-04-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function pinctrl_register() returns ERR_PTR() not NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: artpec6: Remove .owner field for driverWei Yongjun2017-04-261-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove .owner field if calls are used which set it automatically. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: tegra: xusb: Silence sparse warningsThierry Reding2017-04-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 53d2a715c240 ("phy: Add Tegra XUSB pad controller support") added a new driver for the XUSB pad controller that implements a more flexible devicetree binding. In order to preserve backwards compatibility the old driver can be probed if the obsolete bindings are detected. In order to hide the legacy code, these prototypes were defined in a header private to the new driver. This has the disadvantage of making the sparse code checker complain about the missing declarations when compiling the old driver and suggesting to make the functions static. Avoid these sparse warnings by adding local prototype declarations into the compatibility driver. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'sh-pfc-for-v4.12-tag3' of ↵Linus Walleij2017-04-242-15/+19
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.12 (take three) - Miscellaneous fixes for R-Car M2-W and R-Car E2.
| | * | pinctrl: sh-pfc: r8a7794: Swap ATA signalsSergei Shtylyov2017-04-051-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All R8A7794 manuals I have here (0.50 and 1.10) agree that the PFC driver has ATAG0# and ATAWR0# signals in IPSR12 swapped -- fix this. Fixes: 43c4436e2f18 ("pinctrl: sh-pfc: add R8A7794 PFC support") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-13 08:08:05 +0000