summaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'pinctrl-v6.15-1' of ↵Linus Torvalds10 days77-1174/+7656
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Core changes: - None really. New drivers: - AMD ISP411 "AMD ISP" driver - Exynos 2200 and 7870 SoC subdrivers - Sophgo RISC-V SG2042 and SG2044 subdrivers - Amlogic A4 subdriver - Rockchip RK3528 subdriver - Broadcom BCM21664 subdriver - Allwinner A523/T527 subdriver - Ingenic X1600 subdriver - Microchip SAMA7D65 subdriver, essentially a re-branded Atmel AT91 PIO4 driver, but nowadays a Microschip SoC line Improvements: - Bring in the devm_kmemdup_array() helper and use it throughout, also bring in changes to other subsystems for this to establish this helper - Support EGPIO on the Qualcomm SA8775P SoC - Extend EINT support in the Mediatek driver" * tag 'pinctrl-v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (101 commits) pinctrl: mediatek: Add EINT support for multiple addresses pinctrl: amlogic-a4: Drop surplus semicolon pinctrl: nuvoton: Reduce use of OF-specific APIs pinctrl: nuvoton: Convert to use struct group_desc pinctrl: nuvoton: Make use of struct pinfunction and PINCTRL_PINFUNCTION() pinctrl: nuvoton: Convert to use struct pingroup and PINCTRL_PINGROUP() pinctrl: npcm8xx: Fix incorrect struct npcm8xx_pincfg assignment pinctrl: tegra: Fix off by one in tegra_pinctrl_get_group() pinctrl: PINCTRL_AMDISP should depend on DRM_AMD_ISP pinctrl: qcom: sa8775p: Enable egpio function dt-bindings: pinctrl: qcom: Add egpio function for sa8775p pinctrl: qcom: tlmm-test: Validate irq_enable delivers edge irqs pinctrl: qcom: Clear latched interrupt status when changing IRQ type dt-bindings: pinctrl: airoha: Add missing gpio-ranges property pinctrl: bcm281xx: Add missing assignment in bcm21664_pinctrl_lock_all() pinctrl: amd: isp411: Fix IS_ERR() vs NULL check in probe() dt-bindings: pinctrl: at91-pio4: add microchip,sama7d65-pinctrl pinctrl: tegra: Set SFIO mode to Mux Register pinctrl-tegra: Restore SFSEL bit when freeing pins pinctrl: tegra: Add descriptions for SoC data fields ...
| * pinctrl: mediatek: Add EINT support for multiple addressesHao Chang2025-03-245-127/+254
| | | | | | | | | | | | | | | | | | | | For flexible routing, eint will be divided into 5 bases, and it will obtain the operation address through the pins array. Signed-off-by: Hao Chang <ot_chhao.chang@mediatek.com> Signed-off-by: Qingliang Li <qingliang.li@mediatek.com> Link: https://lore.kernel.org/20250322035307.4811-2-ot_chhao.chang@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: amlogic-a4: Drop surplus semicolonLinus Walleij2025-03-221-1/+1
| | | | | | | | | | | | | | | | | | The kernel bots complain about untidy code found using coccinelle, fix it up. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202503212354.Hx2qaDRe-lkp@intel.com/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nuvoton: Reduce use of OF-specific APIsAndy Shevchenko2025-03-204-34/+21
| | | | | | | | | | | | | | | | | | | | | | | | Some drivers are using device property APIs along with OF-specific ones. At the same time few of the latter can be converted to device property calls. Reduce use of OF-specific APIs in order to bring a bit more consistency into the drivers. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250318105932.2090926-6-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nuvoton: Convert to use struct group_descAndy Shevchenko2025-03-201-37/+33
| | | | | | | | | | | | | | | | | | The pin control core header provides struct group_desc. Utilize it instead of open coded variants in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250318105932.2090926-5-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nuvoton: Make use of struct pinfunction and PINCTRL_PINFUNCTION()Andy Shevchenko2025-03-204-35/+17
| | | | | | | | | | | | | | | | | | | | Since pin control provides a generic data type and a macro for the pin function definition, use them in the driver. Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250318105932.2090926-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nuvoton: Convert to use struct pingroup and PINCTRL_PINGROUP()Andy Shevchenko2025-03-202-28/+4
| | | | | | | | | | | | | | | | | | The pin control header provides struct pingroup and PINCTRL_PINGROUP() macro. Utilize them instead of open coded variants in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250318105932.2090926-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: npcm8xx: Fix incorrect struct npcm8xx_pincfg assignmentAndy Shevchenko2025-03-201-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sparse is not happy about implementation of the NPCM8XX_PINCFG() pinctrl-npcm8xx.c:1314:9: warning: obsolete array initializer, use C99 syntax pinctrl-npcm8xx.c:1315:9: warning: obsolete array initializer, use C99 syntax ... pinctrl-npcm8xx.c:1412:9: warning: obsolete array initializer, use C99 syntax pinctrl-npcm8xx.c:1413:9: warning: too many warnings which uses index-based assignment in a wrong way, i.e. it missed the equal sign and hence the index is simply ignored, while the entries are indexed naturally. This is not a problem as the pin numbering repeats the natural order, but it might be in case of shuffling the entries. Fix this by adding missed equal sign and reformat a bit for better readability. Fixes: acf4884a5717 ("pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250318105932.2090926-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: Fix off by one in tegra_pinctrl_get_group()Dan Carpenter2025-03-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This should be >= pmx->soc->ngroups instead of > to avoid an out of bounds access. The pmx->soc->groups[] array is allocated in tegra_pinctrl_probe(). Fixes: c12bfa0fee65 ("pinctrl-tegra: Restore SFSEL bit when freeing pins") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Kunwu Chan <kunwu.chan@linux.dev> Link: https://lore.kernel.org/82b40d9d-b437-42a9-9eb3-2328aa6877ac@stanley.mountain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: PINCTRL_AMDISP should depend on DRM_AMD_ISPGeert Uytterhoeven2025-03-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The AMD Image Signal Processor GPIO pin control functionality is only present on AMD platforms with ISP support, and its platform device is instantiated by the AMD ISP driver. Hence add a dependency on DRM_AMD_ISP, to prevent asking the user about this driver when configuring a kernel that does not support the AMD ISP. Fixes: e97435ab09f3ad7b ("pinctrl: amd: isp411: Add amdisp GPIO pinctrl") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/3685561e8e3cd1d94bce220eeb6001d659da615c.1742306024.git.geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'samsung-pinctrl-6.15' of ↵Linus Walleij2025-03-184-49/+408
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.15 1. Add pin controller drivers for newly usptreamed Samsung Exynos2200 and Exynos7870. 2. Correct filter configuration offset of some of Google GS101 SoC pin banks, which later is supposed to be used during system suspend/resume. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * pinctrl: samsung: add support for eint_fltcon_offsetPeter Griffin2025-03-114-49/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On gs101 SoC the fltcon0 (filter configuration 0) offset isn't at a fixed offset like previous SoCs as the fltcon1 register only exists when there are more than 4 pins in the bank. Add a eint_fltcon_offset and new GS101_PIN_BANK_EINT* macros that take an additional fltcon_offs variable. This can then be used in suspend/resume callbacks to save and restore the fltcon0 and fltcon1 registers. Fixes: 4a8be01a1a7a ("pinctrl: samsung: Add gs101 SoC pinctrl configuration") Cc: stable@vger.kernel.org Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250307-pinctrl-fltcon-suspend-v4-1-2d775e486036@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * pinctrl: samsung: add support for exynos7870 pinctrlKaustabh Chakraborty2025-03-034-0/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Exynos7870 SoC pin-controller in the pinctrl driver. It has 8 GPIO banks, and 3-bit PINCFG_TYPE_DRV width. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://lore.kernel.org/r/20250301-exynos7870-pinctrl-v3-3-ba1da9d3cd2f@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * pinctrl: samsung: add exynos2200 SoC pinctrl configurationIvaylo Ivanov2025-02-193-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the pin-controller found on the Exynos2200 SoC used in Samsung Galaxy S22, S22 Plus and S22 Ultra phones. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20250215113248.159386-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| * | pinctrl: qcom: sa8775p: Enable egpio functionWasim Nazir2025-03-171-24/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Egpio feature allows IsLand Domain IOs to be reused as TLMM GPIOs. sa8775p supports egpio feature for GPIOs ranging from 126 to 148. Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com> Reviewed-by: Dmitry Baryshkov <lumag@kernel.org> Link: https://lore.kernel.org/20250312072509.3247885-3-quic_wasimn@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: tlmm-test: Validate irq_enable delivers edge irqsBjorn Andersson2025-03-171-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 'cf9d052aa600 ("pinctrl: qcom: Don't clear pending interrupts when enabling")' Doug establishes an expectation that edge interrupts occurring while an interrupt is disabled should be delivered once the interrupt is enabled again. Implement a test to validate that this is the case. Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Link: https://lore.kernel.org/20250313-tlmm-test-disabled-irq-delivered-v1-1-f0be903732ac@oss.qualcomm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: Clear latched interrupt status when changing IRQ typeStephan Gerhold2025-03-171-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When submitting the TLMM test driver, Bjorn reported that some of the test cases are failing for GPIOs that not are backed by PDC (i.e. "non-wakeup" GPIOs that are handled directly in pinctrl-msm). Basically, lingering latched interrupt state is still being delivered at IRQ request time, e.g.: ok 1 tlmm_test_silent_rising tlmm_test_silent_falling: ASSERTION FAILED at drivers/pinctrl/qcom/tlmm-test.c:178 Expected atomic_read(&priv->intr_count) == 0, but atomic_read(&priv->intr_count) == 1 (0x1) not ok 2 tlmm_test_silent_falling tlmm_test_silent_low: ASSERTION FAILED at drivers/pinctrl/qcom/tlmm-test.c:178 Expected atomic_read(&priv->intr_count) == 0, but atomic_read(&priv->intr_count) == 1 (0x1) not ok 3 tlmm_test_silent_low ok 4 tlmm_test_silent_high Whether to report interrupts that came in while the IRQ was unclaimed doesn't seem to be well-defined in the Linux IRQ API. However, looking closer at these specific cases, we're actually reporting events that do not match the interrupt type requested by the driver: 1. After "ok 1 tlmm_test_silent_rising", the GPIO is in low state and configured for IRQF_TRIGGER_RISING. 2. (a) In preparation for "tlmm_test_silent_falling", the GPIO is switched to high state. The rising interrupt gets latched. (b) The GPIO is re-configured for IRQF_TRIGGER_FALLING, but the latched interrupt isn't cleared. (c) The IRQ handler is called for the latched interrupt, but there wasn't any falling edge. 3. (a) For "tlmm_test_silent_low", the GPIO remains in high state. (b) The GPIO is re-configured for IRQF_TRIGGER_LOW. This seems to result in a phantom interrupt that gets latched. (c) The IRQ handler is called for the latched interrupt, but the GPIO isn't in low state. 4. (a) For "tlmm_test_silent_high", the GPIO is switched to low state. (b) This doesn't result in a latched interrupt, because RAW_STATUS_EN was cleared when masking the level-triggered interrupt. Fix this by clearing the interrupt state whenever making any changes to the interrupt configuration. This includes previously disabled interrupts, but also any changes to interrupt polarity or detection type. With this change, all 16 test cases are now passing for the non-wakeup GPIOs in the TLMM. Cc: stable@vger.kernel.org Fixes: cf9d052aa600 ("pinctrl: qcom: Don't clear pending interrupts when enabling") Reported-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Closes: https://lore.kernel.org/r/20250227-tlmm-test-v1-1-d18877b4a5db@oss.qualcomm.com/ Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Tested-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/20250312-pinctrl-msm-type-latch-v1-1-ce87c561d3d7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm281xx: Add missing assignment in bcm21664_pinctrl_lock_all()Dan Carpenter2025-03-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The next line checks if this regmap_write() failed, but it doesn't work because the assignment was accidentally left out. Add the assignment. Fixes: 60d69769c851 ("pinctrl: bcm281xx: Add support for BCM21664 pinmux") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Acked-by: Artur Weber <aweber.kernel@gmail.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/dfc15d59-7fa9-4f96-aacb-37c3df6d420d@stanley.mountain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: amd: isp411: Fix IS_ERR() vs NULL check in probe()Dan Carpenter2025-03-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The platform_get_resource() returns NULL on error. It doesn't return error pointers. Fix the error checking to match. Fixes: e97435ab09f3 ("pinctrl: amd: isp411: Add amdisp GPIO pinctrl") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Pratap Nirujogi <pratap.nirujogi@amd.com> Link: https://lore.kernel.org/617f4c77-7837-4e24-9f4d-620ecfedf924@stanley.mountain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: tegra: Set SFIO mode to Mux RegisterPrathamesh Shete2025-03-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra devices have an 'sfsel' bit field that determines whether a pin operates in SFIO (Special Function I/O) or GPIO mode. Currently, tegra_pinctrl_gpio_disable_free() sets this bit when releasing a GPIO. However, tegra_pinctrl_set_mux() can be called independently in certain code paths where gpio_disable_free() is not invoked. In such cases, failing to set the SFIO mode could lead to incorrect pin configurations, resulting in functional issues for peripherals relying on SFIO. This patch ensures that whenever set_mux() is called, the SFIO mode is correctly set in the Mux Register if the 'sfsel' bit is present. This prevents situations where the pin remains in GPIO mode despite being configured for SFIO use. Fixes: 971dac7123c7 ("pinctrl: add a driver for NVIDIA Tegra") Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/20250306050542.16335-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl-tegra: Restore SFSEL bit when freeing pinsPrathamesh Shete2025-03-142-8/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each pin can be configured as a Special Function IO (SFIO) or GPIO, where the SFIO enables the pin to operate in alternative modes such as I2C, SPI, etc. The current implementation sets all the pins back to SFIO mode even if they were initially in GPIO mode. This can cause glitches on the pins when pinctrl_gpio_free() is called. Avoid these undesired glitches by storing the pin's SFIO/GPIO state on GPIO request and restoring it on GPIO free. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/20250305104939.15168-2-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: tegra: Add descriptions for SoC data fieldsPrathamesh Shete2025-03-141-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add detailed descriptions for the remaining fields in the tegra_pinctrl_soc_data structure. This improves code documentation and clarifies the purpose of each field, particularly for the pin-specific configuration options. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/20250305104939.15168-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: spacemit: destroy mutex at driver detachBartosz Golaszewski2025-03-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mutex initialized in probe() is never cleaned up. Use devm_mutex_init() to destroy it automatically. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/20250305102710.52762-1-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: ingenic: jz4730: add pinmux for I2S interfaceH. Nikolaus Schaller2025-03-141-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | I2S is used for the sound codec of the Alpha400. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/7e79b16be569fb0f501032b2b6ec726e4a09411f.1740823241.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: ingenic: jz4730: add pinmux for MIIH. Nikolaus Schaller2025-03-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The MII interface is used for the Ethernet connection of the Alpha400. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/972b31e1fce03808745e53df17315b29e2bcf696.1740823241.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: ingenic: add x1600 supportPaul Boddie2025-03-141-2/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Lumissil/Ingenic X1600 SoC. It uses shadow registers to commit changes to multiple pinctrl registers in parallel. Define specific Chip ID, register offsets, pin tables etc. Handling the unique X1600_GPIO_PU only for the x1600 but not for x1830 and above must be carefully taken into account. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Co-authored-by: Andreas Kemnade <andreas@kemnade.info> Co-authored-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/84477ec9cb9ed13bf4f6f87d5fb3b55542d31097.1740823241.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Add support for the secondary A523 GPIO portsAndre Przywara2025-03-133-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As most other Allwinner SoCs before, the A523 chip contains a second GPIO controller, managing banks PL and PM. Use the newly introduced DT based pinctrl driver to describe just the generic pinctrl properties, so advertise the number of pins per bank and the interrupt capabilities. The actual function/mux assignment is taken from the devicetree. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-9-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Add support for the Allwinner A523Andre Przywara2025-03-133-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A523 contains pins in 10 out of the 11 possible pin banks; it just skips port A. Use the newly introduced DT based pinctrl driver to describe just the generic pinctrl properties, so advertise the number of pins per bank and the interrupt capabilities. The actual function/mux assignment is taken from the devicetree. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-8-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: allow reading mux values from DTAndre Przywara2025-03-133-0/+384
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far every Allwinner SoC needs a large table in the kernel code, to describe the mapping between the pinctrl function names ("uart") and the actual pincontroller mux value to be written into the registers. This adds a lot of data into a single image kernel, and also looks somewhat weird, as the DT can easily store the mux value. Add some code that allows to avoid that table: the struct that describes the existing pins will be build at *runtime*, based on very basic information provided by the respective SoC's pinctrl driver. This consists of the number of pins per bank, plus information which bank provides IRQ support, along with the mux value to use for that. The code will then iterate over all children of the pincontroller DT node (which describe each pin group), and populate that struct with the mapping between function names and mux values. The only thing that needs adding in the DT is a property with that value, per pin group. When this table is built, it will be handed over to the existing sunxi pinctrl driver, which cannot tell a difference between a hardcoded struct and this new one built at runtime. It will take care of registering the pinctrl device with the pinctrl subsystem. All a new SoC driver would need to do is to provide two arrays, and then call the sunxi_pinctrl_dt_table_init() function. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-6-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: support moved power configuration registersAndre Przywara2025-03-132-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner pincontroller IP features some registers to control the withstand voltage of each pin group. So far those registers were always located at the same offset, but the A523 SoC has moved them (probably to accommodate all eleven pin banks). Add a flag to note this feature, and use that to program the registers either at offset 0x340 or 0x380. So far no pincontroller driver uses this flag, but we need it for the upcoming A523 support. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-5-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: move bank K register offsetAndre Przywara2025-03-132-8/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner pincontroller register layout used to allow for at least 11 banks per controller, any more banks would reside at a second controller instance. When the per-bank register map size was increased with the D1, it turned out that the last bank (port K) of those maximum 11 banks actually would not fit anymore in the 512 bytes reserved for the pincontroller registers. On new SoCs Allwinner thus moved the last bank beyond the existing registers, at offset 0x500. So far SoCs never used more than 9 banks per controller, but the new Allwinner A523 actually uses all 11 banks. Since that SoC also uses the extended layout, its PortK needs to be programmed at offset 0x500. Factor out the bank offset calculation into a new function, and handle the case for the last bank separately. Since none of the older SoCs ever used PortK, we can ignore this case, and just always use offset 0x500 for the last bank. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/20250306235827.4895-4-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: increase number of GPIO bank regulatorsAndre Przywara2025-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By design, the Allwinner pinctrl IP always supported up to 11 GPIO banks, though no SoC ever used more than 9 banks so far. The Allwinner A523 has pins in all 11 banks, which exceeds the number of per-bank regulators that we currently support, as this was set to 9. Increase the size of the array to hold up to 11 regulator structs, to support pins in bank J and K as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/20250306235827.4895-3-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: refactor pinctrl variants into flagsAndre Przywara2025-03-137-34/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some Allwinner SoCs we have one pinctrl driver caring for multiple very similar chips, and are tagging certain pins with a variant bitmask. The Allwinner D1 introduced a slightly extended register layout, and we were abusing this variant mask to convey this bit of information into the common code part. Now there will be more pinctrl device properties to consider (has PortF voltage switch, for instance), so shoehorning this into the variant bitmask will not fly anymore. Refactor the "variant" field into a more generic "flags" field. It turns out that we don't need the variant bits to be unique across all SoCs, but only among those SoCs that share one driver (table), of which there are at most three variants at the moment. So the actual variant field can be limited to say 8 bits, and the other bits in the flag register can be re-purposed to hold other information, like this extended register layout. As a side effect we can move the variant definition into the per-SoC pinctrl driver file, which makes it more obvious that this is just a private definition, only relevant for this particular table. This also changes the artificial sun20i-d1 "variant" into the actual flag bit that we are after. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-2-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'intel-pinctrl-v6.15-1' of ↵Linus Walleij2025-03-137-23/+21
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.15-1 * Introduce devm_kmemdup_array() and convert Intel pin control drivers * Update PWM handling for the cases when it's provided by Intel pin control * Miscellaneous fixes, updates, and cleanups The following is an automated git shortlog grouped by driver: baytrail: - copy communities using devm_kmemdup_array() - Use dedicated helpers for chained IRQ handlers cherryview: - use devm_kmemdup_array() devres: - Introduce devm_kmemdup_array() driver core: - Split devres APIs to device/devres.h err.h: - move IOMEM_ERR_PTR() to err.h iio: - adc: xilinx-xadc-core: use devm_kmemdup_array() - imu: st_lsm9ds0: Replace device.h with what is needed input: - ipaq-micro-keys: use devm_kmemdup_array() - sparse-keymap: use devm_kmemdup_array() intel: - drop repeated config dependency - copy communities using devm_kmemdup_array() - Fix wrong bypass assignment in intel_pinctrl_probe_pwm() - Import PWM_LPSS namespace for devm_pwm_lpss_probe() lynxpoint: - Use dedicated helpers for chained IRQ handlers MAINTAINERS: - Add pin control and GPIO to the Intel MID record pwm: - lpss: Clarify the bypass member semantics in struct pwm_lpss_boardinfo - lpss: Actually use a module namespace by defining the namespace earlier pxa2xx: - use devm_kmemdup_array() tangier: - use devm_kmemdup_array() Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: intel: drop repeated config dependencyRaag Jadav2025-03-031-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already have ACPI dependency for Intel pinctrl menu. No need to repeat it. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | Merge tag 'ib-devres-iio-input-pinctrl-v6.15' into intel/pinctrlAndy Shevchenko2025-02-255-18/+12
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a few Intel pin control drivers that are affected by the devm_kmemdup_array() conversion, merge the ib-devres-iio-input-pinctrl for making development going smoothly. * Split devres APIs to a separate header (linux/device/devres.h) * Move IOMEM_ERR_PTR() to err.h to avoid unneeded loops * Introduce devm_kmemdup_array() * Use devm_kmemdup_array() in input, IIO, and pinctrl subsystems Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | | * | pinctrl: pxa2xx: use devm_kmemdup_array()Raag Jadav2025-02-241-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert to use devm_kmemdup_array() which is more robust. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | | * | pinctrl: tangier: use devm_kmemdup_array()Raag Jadav2025-02-241-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert to use devm_kmemdup_array() and while at it, use source size instead of destination. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | | * | pinctrl: cherryview: use devm_kmemdup_array()Raag Jadav2025-02-241-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert to use devm_kmemdup_array() and while at it, use source size instead of destination. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | | * | pinctrl: baytrail: copy communities using devm_kmemdup_array()Raag Jadav2025-02-241-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copy communities using devm_kmemdup_array() instead of doing it manually. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | | * | pinctrl: intel: copy communities using devm_kmemdup_array()Raag Jadav2025-02-241-4/+2
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copy communities using devm_kmemdup_array() instead of doing it manually. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | pinctrl: intel: Fix wrong bypass assignment in intel_pinctrl_probe_pwm()Andy Shevchenko2025-02-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When instantiating PWM, the bypass should be set to false. The field is used for the selected Intel SoCs that do not have PWM feature enabled in their pin control IPs. Fixes: eb78d3604d6b ("pinctrl: intel: Enumerate PWM device when community has a capability") Reported-by: Alexis GUILLEMET <alexis.guillemet@dunasys.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Alexis GUILLEMET <alexis.guillemet@dunasys.com>
| | * | pinctrl: intel: Import PWM_LPSS namespace for devm_pwm_lpss_probe()Uwe Kleine-König2025-02-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel pinctrl driver can provide a PWM device and for that needs to call the function devm_pwm_lpss_probe(). That function is provided by the pwm-lpss driver which intends to export it in the "PWM_LPSS" namespace. To prepare fixing the pwm-lpss driver to indeed use the "PWM_LPSS" namespace, import that namespace when used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | pinctrl: lynxpoint: Use dedicated helpers for chained IRQ handlersAndy Shevchenko2025-02-031-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of relying on the fact that the parent IRQ chip supports fasteoi mode and calling the respective callback at the end of the interrupt handler, surround it with enter and exit helpers for chained IRQ handlers which will consider all possible cases. This in particular unifies how GPIO drivers handle IRQ. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | pinctrl: baytrail: Use dedicated helpers for chained IRQ handlersAndy Shevchenko2025-02-031-1/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of relying on the fact that the parent IRQ chip supports fasteoi mode and calling the respective callback at the end of the interrupt handler, surround it with enter and exit helpers for chained IRQ handlers which will consider all possible cases. This in particular unifies how GPIO drivers handle IRQ. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | Merge tag 'renesas-pinctrl-for-v6.15-tag2' of ↵Linus Walleij2025-03-133-0/+6
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.15 (take two) - Add missing of_node_put() calls. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: renesas: rza2: Fix missing of_node_put() callFabrizio Castro2025-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_parse_phandle_with_fixed_args() requires its caller to call into of_node_put() on the node pointer from the output structure, but such a call is currently missing. Call into of_node_put() to rectify that. Fixes: b59d0e782706 ("pinctrl: Add RZ/A2 pin and gpio controller") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250305163753.34913-5-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: rzv2m: Fix missing of_node_put() callFabrizio Castro2025-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_parse_phandle_with_fixed_args() requires its caller to call into of_node_put() on the node pointer from the output structure, but such a call is currently missing. Call into of_node_put() to rectify that. Fixes: 92a9b8252576 ("pinctrl: renesas: Add RZ/V2M pin and gpio controller driver") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250305163753.34913-4-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: rzg2l: Fix missing of_node_put() callFabrizio Castro2025-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_parse_phandle_with_fixed_args() requires its caller to call into of_node_put() on the node pointer from the output structure, but such a call is currently missing. Call into of_node_put() to rectify that. Fixes: c4c4637eb57f ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250305163753.34913-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | pinctrl: bcm281xx: Add support for BCM21664 pinmuxArtur Weber2025-03-051-2/+688
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BCM21664 is another chip from the Kona line of Broadcom SoCs, and its pinmux shares a lot of similarities with the BCM281xx pinmux. Add support for the BCM21664 pinmux controller to the BCM281xx driver. This also enables pinmux support for the BCM23550, which has an identical pinmux config to the BCM21664 (hence they can share a single compatible, brcm,bcm21664-pinctrl). Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/20250303-bcm21664-pinctrl-v3-4-5f8b80e4ab51@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 13:34:58 +0000