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| | * pinctrl: tigerlake: Revert "Add Alder Lake-M ACPI ID"Andy Shevchenko2022-02-231-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It appears that last minute change moved ACPI ID of Alder Lake-M to the INTC1055, which is already in the driver. This ID on the other hand will be used elsewhere. This reverts commit 258435a1c8187f559549e515d2f77fa0b57bcd27. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: baytrail: Clear direct_irq_en flag on broken configsHans de Goede2022-01-241-2/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards set the direct_irq_en flag in the conf0 register without setting the correct trigger bits. The direct_irq_en flag just means that the GPIO will send IRQs directly to the APIC instead of going through the shared interrupt for the GPIO controller, in order for the pin to be able to actually generate IRQs the trigger flags must configure the IRQ as a level-high or level-low active IRQ. Note testing shows that using edge trigger add the conf0 register level does NOT work, instead edge triggering should be set at the IO-APIC level. I believe that the direct_irq_en flag connects the output of the GPIO's IRQ trigger block, which normally sets the status flag in the IRQ status reg at 0x800 to one of the IO-APIC pins according to the direct IRQ mux. This means that the TRIG_LVL bit *must* be set, so that the GPIO's input value is directly passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, selecting edge mode operation then on the first edge the selected IO-APIC pin goes high, but since no write-to-clear write will be done to the IRQ status reg at 0x800, the detected edge condition will never get cleared. This APIC pin stuck high condition can be observed with the pin configured as level-high active, in the form of an interrupt storm. Clearing the TRIG_MASK bits of conf0 stops the storm, reconfiguring them as edge again results in a storm again as soon as the edge is triggered once. Detect invalid trigger flags, log a FW_BUG warning when encountering this and clear the direct_irq_en flag so that a driver can actually use the pin as IRQ through gpiod_to_irq(). Specifically this allows the edt-ft5x06 touchscreen driver to use INT33FC:02 pin 3 as touchscreen IRQ on the Nextbook Ares 8 tablet, accompanied by the following new log message byt_gpio INT33FC:02: [Firmware Bug]: pin 3: direct_irq_en set without trigger, clearing The new byt_direct_irq_sanity_check() function also checks that the pin is actually appointed to one of the 16 direct-IRQs which the GPIO controller supports and on success prints debug messages like these: byt_gpio INT33FC:02: Pin 0: uses direct IRQ 0 (IO-APIC 67) byt_gpio INT33FC:02: Pin 15: uses direct IRQ 2 (IO-APIC 69) This is useful to figure out the GPIO pin belonging to ACPI resources like this one: "Interrupt () { 0x00000043 }" or the other way around. The strict checking of valid trigger flags this introduces does result in FW_BUG messages on quite a few devices. E.g. on the Yoga Tablet 2 1051L: byt_gpio INT33FC:00: [Firmware Bug]: pin 92: direct_irq_en set but no IRQ assigned, clearing byt_gpio INT33FC:00: [Firmware Bug]: pin 93: direct_irq_en set but no IRQ assigned, clearing These 2 also have mux set to 7 and fall + rise + level trigger bits set, presumably something has written 0xffffffff to their conf0 registers byt_gpio INT33FC:02: Pin 3: uses direct IRQ 1 (IO-APIC 68) byt_gpio INT33FC:02: [Firmware Bug]: pin 3: direct_irq_en set without trigger (conf0: 2803cc00h), clearing Most tablets seem to have this, looking at DSDTs this seems intended for use with an I2C HID sensor-hub and is still set on devices without one. To make sure this does not cause any regressions this has been tested, including checking disabled direct-IRQs are not used in the DSDT, on the following devices: Asus ME176C Asus TF103C Chuwi Vi10 (with its Windows BIOS) HP x2 10-n000nd Lenovo Yoga Tablet 2 1050L (Android version, without EC, with buggy DSDT) Lenovo Yoga Tablet 2 1051L (Windows version, with EC) Suggested-by: Andy Shevchenko <andy@kernel.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | Merge tag 'renesas-pinctrl-for-v5.18-tag2' of ↵Linus Walleij2022-02-2731-3126/+3914
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.18 (take two) - Share more pin group data, to reduce kernel size and ease review, - Improve the pin control table validator, - Add support for the new R-Car S4-8 SoC, - Miscellaneous fixes and improvements.
| | * | pinctrl: renesas: r8a779f0: Add Ethernet pins, groups, and functionsGeert Uytterhoeven2022-02-251-0/+288
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and functions for the Ethernet Time-Sensitive Networking (TSN) interfaces on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/e0a1dc7d2435d28811e3acb361dae050eb3aabc9.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a779f0: Add QSPI pins, groups, and functionsGeert Uytterhoeven2022-02-251-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and functions for the Quad SPI Controllers on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/cd7f7feeabebf268adc9e050e348230e93b40829.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a779f0: Add PCIe pins, groups, and functionGeert Uytterhoeven2022-02-251-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and function for the PCIe Controllers on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/b2f95db490d13e8cb7d97a63d58d47933317e28a.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a779f0: Add MSIOF pins, groups, and functionsGeert Uytterhoeven2022-02-251-0/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and function for the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/c625769714b1027a756dd2ed4a017eb24708a041.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a779f0: Add MMC pins, groups, and functionGeert Uytterhoeven2022-02-251-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and function for the MMC interface on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/81a35c1fac4616d25501942848eb9662d477f9ef.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a779f0: Add INTC-EX pins, groups, and functionGeert Uytterhoeven2022-02-251-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/dc6e25da42ac4bd19ca31b5b32b43a10a0e1aa7e.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a779f0: Add HSCIF pins, groups, and functionsGeert Uytterhoeven2022-02-251-0/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and functions for the High Speed Serial Communication Interfaces with FIFO (HSCIF) on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/2b85b8857c1189fa6ee33e2f57fe746d740481d1.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a779f0: Add I2C pins, groups, and functionsGeert Uytterhoeven2022-02-251-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and functions for the I2C Bus Interfaces (I2C) on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/217f5b3e3888b5899c375d3cb1ec8780f6a9e19b.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a779f0: Add SCIF pins, groups, and functionsGeert Uytterhoeven2022-02-251-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and functions for the Serial Communication Interfaces with FIFO (SCIF) on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/6369359a53483291ee536787c8a232462ff1b3a9.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: Initial R8A779F0 PFC supportGeert Uytterhoeven2022-02-255-0/+1037
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial Pin Function Controller (PFC) support for the Renesas R-Car S4-8 (R8A779F0) SoC, including bias, drive strength and voltage control. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/fd8201da404b7b0897130b254380ffc97f437266.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: Add PORT_GP_CFG_19 macrosGeert Uytterhoeven2022-02-251-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PORT_GP_CFG_19() and PORT_GP_19() helper macros, to be used by the r8a779f0 subdriver. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/f7fc711d065f78911bac1b616880ba3dbc858158.1645457792.git.geert+renesas@glider.be
| | * | pinctrl: renesas: Remove unneeded #include <linux/gpio.h>Geert Uytterhoeven2022-02-245-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linus reports that some Renesas pin control sub-drivers are still including <linux/gpio.h> instead of <linux/gpio/driver.h>. As these sub-drivers don't need either, the includes can just be removed. Reported-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/578825d779b45af745cc7623c7f69d2ddeadac4b.1645605227.git.geert+renesas@glider.be
| | * | pinctrl: renesas: checker: Fix miscalculation of number of statesGeert Uytterhoeven2022-02-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The checker failed to validate all enum IDs in the description of a register with fixed-width register fields, due to a miscalculation of the number of described states: each register field of n bits can have "1 << n" possible states, not "1". Increase SH_PFC_MAX_ENUMS accordingly, now more enum IDs are checked (SH-Mobile AG5 has more than 4000 enum IDs defined). Fixes: 12d057bad683b1c6 ("pinctrl: sh-pfc: checker: Add check for enum ID conflicts") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6d8a6a05564f38f9d20464c1c17f96e52740cf6a.1645460429.git.geert+renesas@glider.be
| | * | pinctrl: renesas: checker: Check drive pin conflictsGeert Uytterhoeven2022-02-221-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check that there is only a single entry for each pin with drive strength capabilities. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/382206e737710afd3059abe75bc41e324823e657.1640270559.git.geert+renesas@glider.be
| | * | pinctrl: renesas: checker: Check bias pin conflictsGeert Uytterhoeven2022-02-221-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check that there is only a single entry for each pin with pull-up and/or pull-down capabilities. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/dbda76f342258f8029f0420fbe3f341a9abd6f01.1640270559.git.geert+renesas@glider.be
| | * | pinctrl: renesas: checker: Validate I/O voltage configs consistencyGeert Uytterhoeven2022-02-221-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Validate consistency of the pin control tables for pins with I/O voltage capabilities. If a pin has I/O voltage register bits declarations through .pin_to_pocctrl(), the SH_PFC_PIN_CFG_IO_VOLTAGE flag should be set in the pin's configs, and vice versa. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/de81cced01ae3f26d341177d66d4b8e918fbfb76.1640270559.git.geert+renesas@glider.be
| | * | pinctrl: renesas: checker: Validate drive strength configs consistencyGeert Uytterhoeven2022-02-221-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Validate consistency of the pin control tables for pins with drive strength capabilities. If a pin has drive strength register bits declarations in drive_regs[], the SH_PFC_PIN_CFG_DRIVE_STRENGTH flag should be set in the pin's configs, and vice versa. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0d5de01b5fe2c5fd23c3bea41077dc57ad105b9e.1640270559.git.geert+renesas@glider.be
| | * | pinctrl: renesas: checker: Validate bias configs consistencyGeert Uytterhoeven2022-02-221-7/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Validate consistency of the pin control tables for pins with pull-up and/or pull-down capabilities. If a pin has bias register bits declarations in bias_regs[] or through .pin_to_portcr(), the corresponding SH_PFC_PIN_CFG_PULL* flags should be set in the pin's configs, and vice versa, and the .get_bias() and .set_bias() callbacks should be implemented. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/19b3e0773fbb36c015a43db683f79e75b0fec3ee.1640270559.git.geert+renesas@glider.be
| | * | pinctrl: renesas: checker: Add pin group sharing checksGeert Uytterhoeven2022-02-221-5/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add checks for discovering pin groups that could share pin data, as sharing reduces kernel size. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e16fdf729156e13b591d2f082f2cc934da580074.1640270559.git.geert+renesas@glider.be
| | * | pinctrl: renesas: checker: Simplify same_name()Geert Uytterhoeven2022-02-221-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the helper that checks if two strings are valid and identical. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/509c70041bcf4302e284758abe1fd8165644b505.1640270559.git.geert+renesas@glider.be
| | * | pinctrl: renesas: Pass sh_pfc_soc_info to rcar_pin_to_bias_reg()Geert Uytterhoeven2022-02-223-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently rcar_pin_to_bias_reg() takes a struct sh_pfc pointer, which is only available after the pin control driver has been initialized, thus preventing the checker from calling this function for validating consistency of the pin control tables. Fix this by replacing the parameter by a struct sh_pfc_soc_info pointer. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/3065a12dde606bacec9e5f14f10cabeaae75e265.1640270559.git.geert+renesas@glider.be
| | * | pinctrl: renesas: Factor out .pin_to_portcr() address handlingGeert Uytterhoeven2022-02-225-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All implementations of the .pin_to_portcr() method implement the same conversion from Port Control Register offset to virtual address. Factor it out into the two callers. Remove the pfc parameter, as it is no longer used. Note that the failure handling in r8a7740_pin_to_portcr() is pro forma, as the function is never called with an invalid pin number. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a485d4986a17259256988eb14e3a4c2b8d61c303.1640270559.git.geert+renesas@glider.be
| | * | pinctrl: renesas: Remove unused pfc parameter from .pin_to_pocctrl()Geert Uytterhoeven2022-02-2215-25/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pfc parameter of the .pin_to_pocctrl() method was never used. It is a relic of the old I/O voltage handling before commit 8775306dcf48092f ("pinctrl: sh-pfc: refactor voltage setting"). Remove the parameter, as it prevents the checker from calling this function for validating consistency of the pin control tables. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/822133086f32618c7fc920123c6a96f5d4ea7ad6.1640270559.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a77990: Share more VIN pin group dataGeert Uytterhoeven2022-02-221-30/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin group vin4_g8 is a subset of vin4_data24_a. Pin group vin5_high8 is a subset of vin5_data16_a. This reduces kernel size by 128 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cfb71c90c19723ba2770f7512f138e4b17857141.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a77965: Share more VIN pin group dataGeert Uytterhoeven2022-02-221-30/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin group vin4_g8 is a subset of vin4_data24_a. Pin group vin5_high8 is a subset of vin5_data16. This reduces kernel size by 128 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/fd8779f5c7a397e8e4dc3604fe2af55e250a9f40.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7796: Share more VIN pin group dataGeert Uytterhoeven2022-02-221-26/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin group vin4_g8 is a subset of vin4_data24_a. Pin group vin5_high8 is a subset of vin5_data16. This reduces kernel size by 128 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1fc04bb08e2c26109509bd53b19ffbf9ce83d2f1.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a77951: Share more VIN pin group dataGeert Uytterhoeven2022-02-221-26/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin group vin4_g8 is a subset of vin4_data24_a. Pin group vin5_high8 is a subset of vin5_data16. This reduces kernel size by 128 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/100605798d02cbd8695aedfaaaa8a3b63e3a281f.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7790: Share more VIN pin group dataGeert Uytterhoeven2022-02-221-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin group vin2_g8 is a subset of vin2_data24. This reduces kernel size by 64 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a4f6a70344654456abea1f15539219d1e02a74fe.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7790: Share USB1 pin group dataGeert Uytterhoeven2022-02-221-19/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin group usb0_ovc_vbus is a subset of usb0. Pin group usb1_pwen is a subset of usb1. This reduces kernel size by 16 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/b9f37cf00064293b4b6f9068bda8c1ab819090f5.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: emev2: Share SDI pin group dataGeert Uytterhoeven2022-02-221-41/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdi0_data[14] are subsets of sdi0_data8. Pin groups sdi[12]_data1 are subsets of sdi[12]_data4. This reduces kernel size by 56 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0f35f01666748217b93c2debc0098f9442061a1a.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: sh73a0: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-33/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[012]_data1 are subsets of sdhi[012]_data4. This reduces kernel size by 24 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/96a5be0c34c66b302e16e915a7cc6272783aa73c.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a77990: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-51/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[01]_data1 are subsets of sdhi[01]_data4. Pin groups sdhi3_data[14] are subsets of sdhi3_data8. This reduces kernel size by 56 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2f702b6c6114458a43a77ae04089e7f9e20482e5.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7796: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-64/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[01]_data1 are subsets of sdhi[01]_data4. Pin groups sdhi[23]_data[14] are subsets of sdhi[23]_data8. This reduces kernel size by 96 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/b638b7ad4a874e64a35057fa1ce6ab23db3406cf.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a77965: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-76/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[01]_data1 are subsets of sdhi[01]_data4. Pin groups sdhi[23]_data[14] are subsets of sdhi[23]_data8. This reduces kernel size by 96 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d40b65eaf5e18856b6df53a1b787a1432ef14dd2.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a77951: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-64/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[01]_data1 are subsets of sdhi[01]_data4. Pin groups sdhi[23]_data[14] are subsets of sdhi[23]_data8. This reduces kernel size by 96 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f15024a4984f4b13e1171e3c40df9c6f7b672d7b.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a77950: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-64/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[01]_data1 are subsets of sdhi[01]_data4. Pin groups sdhi[23]_data[14] are subsets of sdhi[23]_data8. This reduces kernel size by 96 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/4a479a1126bb405dbc853f328d483f649d43c61e.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7794: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-33/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[012]_data1 are subsets of sdhi[012]_data4. This reduces kernel size by 24 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e4d831e163010d2b62ecc20f8e4b79fd298b2172.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7792: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-11/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin group sdhi0_data1 is a subset of sdhi0_data4. This reduces kernel size by 8 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/76a245f8b39f8e71e3311868ec15ce8c9c44bde0.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7791: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-33/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[012]_data1 are subsets of sdhi[012]_data4. This reduces kernel size by 24 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cb39cb8fe9152197df56f70b4b146d8fe96fb0b7.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7790: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-44/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[0-3]_data1 are subsets of sdhi[0-3]_data4. This reduces kernel size by 32 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/88a3c2b09d34f2a528ecaa1bd55b6a96e156f5b1.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7779: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-44/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[0-3]_data1 are subsets of sdhi[0-3]_data4. This reduces kernel size by 32 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/01fd254a90be16bf37be5ecd20ada0ab2b50abd2.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7778: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-31/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin group sdhi0_data1 is a subset of sdhi0_data4. Pin groups sdhi[12]_data1_[ab] are subsets of sdhi[12]_data4_[ab]. This reduces kernel size by 40 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/997df5b8a01657ede685c0869d73e4d6b71dce26.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a77470: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-22/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[02]_data1 are subsets of sdhi[02]_data4. This reduces kernel size by 16 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9888bbd36ec207d6e5ece6c661e2fb8bc05a7dd6.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a7740: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-33/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[012]_data1 are subsets of sdhi[012]_data4. This reduces kernel size by 24 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e07ae7b52efba55cc210d52de6a771129dd8a3b0.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a73a4: Share SDHI pin group dataGeert Uytterhoeven2022-02-221-33/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups sdhi[012]_data1 are subsets of sdhi[012]_data4. This reduces kernel size by 24 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/fca0b9c7cc5a1b4dd8d9bf4eff35d88d37eeab21.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a77980: Share RPC pin group dataGeert Uytterhoeven2022-02-221-46/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups qspi[01]_data[24] are subsets of rpc_data. Pin group rpc_clk1 is a subset of rpc_clk2. This reduces kernel size by 104 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6da6ef4184939a0793ca5fd805e9f6bc6c07a095.1640269757.git.geert+renesas@glider.be
| | * | pinctrl: renesas: r8a77970: Share RPC pin group dataGeert Uytterhoeven2022-02-221-46/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin groups qspi[01]_data[24] are subsets of rpc_data. Pin group rpc_clk1 is a subset of rpc_clk2. This reduces kernel size by 104 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a71da3daa818a33c1e81bff07d643d3f30ff1b7d.1640269757.git.geert+renesas@glider.be
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 04:19:19 +0000